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| 型號： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁數(shù)： | 99/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
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330
3.4.39.4 DRF Control Register 3 at CCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_destination_offset_lo
R/W
DRF receive destination start offset low. DRF_destination_offset_lo specifies the transferred
destination offset low.
3.4.40 DRF Control Registers at C0h, C4h, C8h, and CCh (DRPktz at 90h = 1)—Packetizer
When DRPktz is set to 1, the DRF control registers describe the packetizer mode. The packetizer mode is primarily
used with SBP-2. These registers default to 0000 0000h and, except for the bits specified, are unaffected by a bus
reset.
3.4.40.1 DRF Control Register 0 at C0h
BITS
ACRONYM
DIR
DESCRIPTION
01
DRFCTL[0:1]
R/W
DRF packetizer transmit control. Table 33 describes the read and write values of these control bits.
2
DRFClr/DRFst
R/W
DRF clear control bit (write) / DRF status transmit (read)
When DRFClr is set to 1, the DRF data is cleared. This bit is automatically set to 0 when the DRF is cleared.
DRFClr must not be asserted when DRFCtl is busy. When DRFst is set to 0, the read value specifies the
current transaction status.
3
DRFNdIdval
R/O
DRF NodeID valid. This bit represents a valid NodeID in DRF destination ID. This bit is 1 when the
destination ID at C8h is changed. This bit defaults to 0 and is set to 0 on a bus reset.
4
DRFNotify
R/W
DRF notify. When this bit is set to 1, transaction status data is transferred following a DRF data transfer.
5
Reserved
N/A
Reserved
67
DRFSpd
R/W
DRF transaction speed. DRFSpd specifies the speed used by the DRF packetizer.
00 : 100 Mbps
01 : 200 Mbps
10 : 400 Mbps
11 : Not valid
811
DRF Max Payload
R/W
DRF transfer maximum payload. DRFMaxPayload is used to calculate the maximum data transfer length
that the DRF packetizer requests in a single read transaction. The maximum data transfer length is
specified as 2(DRFMaxPayload + 2) .
12
PgTblEn
R/W
Page table enable. PgTblEn controls page table fetching. When PgTblEn is set to 1, page table fetching is
enabled. DRF_destination_offset_hi and DRF_destination_offset_lo data point to the page table address.
When PgTblEn is 0 and AutoPg is set to 1, page table fetching is disabled. DRF_destination_offset_hi and
DRF_destination_offset_lo are data areas.
1315
DRF Page Size
R/W
DRF receive page size. DRF Page Size specifies the underlying page size of data buffer memory. Any one
request packet is not permitted to cross a page boundary. DRF Page Size value of zero indicates that the
underlying page size is not specified. Otherwise, the page size is 2(DRFPageSize + 8).
1631
DRF_BlockSize/
DRF_BlockCount
R/W
DRF transmit block size / DRF transmit block count. When LngBlk in DMA control (90h) is set to 0, this
value is the DRF_BlockSize. DRF_BlockSize specifies the transmitted blocksize value in bytes. When
LngBlk is set to 1, the value is the DRF_BlockCount. DRF_BlockCount specifies the number of transmitted
blocks. DRF_BlockCount is decremented during transmission automatically.
Table 33. DRFCtl: DRF Packetizer Transmit Control
READ VALUE
WRITE VALUE
DRFCTL0
DRFCTL1
STATE
DRFCTL0
DRFCTL1
STATE
0
IDLE
0
No operation
1
0
BUSY
1
0
Start/restart
1
PEND
1
Init-start
0
1
PAGEFAULT
0
1
Abort
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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