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| 型號(hào)： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁數(shù)： | 30/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
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113
Table 112. Base Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Physical ID
6
R
This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid
after a bus reset until self-ID has completed as indicated by an unsolicited page-0 register (Table 113) status
transfer.
R
1
R
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by a bus reset, and is set to 1 during
tree-ID if this node becomes root.
CPS
1
R
Cable-power status. This bit indicates the state of the CPS input pin. The CPS pin is normally tied to serial bus
cable power through a 400-k
resistor. A 0 in this bit indicates that the cable power voltage has dropped below
its threshold for assured reliable operation.
RHB
1
R/W
Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is
reset to 0 by hardware reset and is unaffected by bus reset.
IBR
1
R/W
Initiate bus reset. This bit instructs the PHY to initiate a long (166
s) bus reset at the next opportunity. Any
receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR
bit is reset to 0 by hardware reset or bus reset.
Gap_Count
6
R/W
Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. The
gap count may be set either by a write to this field or by reception or transmission of a PHY_CONFIG packet.
The gap count is set to 3Fh by a hardware reset or after two consecutive bus resets without an intervening write
to the Gap_Count field (either by a write to the PHY register or by a PHY_CONFIG packet).
Extended
3
R
Extended register definition. For the TSB43AA82 this field is 111b, indicating that the extended register set is
implemented.
Num_Ports
5
R
Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB43AA82 this field
is 00010b.
PHY_Speed
3
R
PHY speed capability. For the TSB43AA82 PHY this field is 010b, indicating s400 speed capability.
Delay
4
R
PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed as
144+(delay*20) ns. For the TSB43AA82 this field is 0.
LCtrl
1
R/W
Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The
logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is
considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software
controllable means to indicate the LLC active status in lieu of using the LPS input.
The LCtrl bit is set to 1 by a hardware reset and is unaffected by a bus reset.
Note: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the
LCtrl bit. If the PHY-LLC interface is operational as determined by an active LPS input, then the received
packets and status information continue to be presented on the interface, and any requests indicated on the
LREQ input are processed, even if the LCtrl bit is cleared to 0.
C
1
R/W
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager.
This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by the
CONTEND input pin upon hardware reset and is unaffected by a bus reset.
Jitter
3
R
PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater
data delay, expressed as (Jitter+1)*20 ns. For the TSB43AA82 this field is 0.
Pwr_Class
3
R/W
Node power class. This field indicates this node’s power consumption and source characteristics, and is
replicated in the pwr field (bits 21–23) of the self-ID packet. This field is set to the state specified by the
PWRCLS0–PWRCLS2 input pins upon hardware reset and is unaffected by a bus reset. See Table 119.
WDIE
1
R/W
Watch dog interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever
resume operations begin on any port. This bit also enables the LINKON output signal to be activated whenever
the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is reset to 0 by hardware
reset and is unaffected by a bus reset.
ISBR
1
R/W
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.30
s) arbitrated bus
reset at the next opportunity. This bit is cleared to 0 by a bus reset.
Note: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus
reset being performed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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