參數(shù)資料
型號： TSB43AA82GGW
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176
封裝： PLASTIC, BGA-176
文件頁數(shù)： 77/146頁
文件大?。?/td> 770K
代理商： TSB43AA82GGW
310
BITS
DESCRIPTION
DIR
ACRONYM
27
CORend
S/C
Command block ORB fetch completed. When the fetched command block ORB is stored in the CRF,
CORend is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next transaction begins.
28
DTFEnd
S/C
DMA transaction from DTF completed. When the transactions of all blocks from DTF are complete,
DTFEnd is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next transaction begins.
29
DRFEnd
S/C
DMA transaction from DRF completed. When the transactions of all blocks from DRF are complete,
DRFEnd is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next process begins.
30
TxExpr
S/C
Transmitter expired. When the transmitter fails to transfer the packets, TxExpr is set to 1.
31
AgntWr
S/C
Agent written. When the registers of any agent, command or management, are written to, AgntWr is set to
1. The host can read State, DrBll and UnSEn from the agent status register (5Ch) and
ORB_destination_offset_hi and ORB_destination_offset_lo from the ORB pointer registers (54h, 58h).
3.4.5
Cycle Timer Register at 14h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
06
Seconds_Count
R/W
Cycle seconds count. When Cycle_Count rolls over, Seconds_Count is incremented.
719
Cycle_Count
R/W
Cycle count counting 125
s. When Cycle_Offset rolls over, Cycle_Count is incremented.
2031
Cycle_Offset
R/W
Cycle offset counting 40 ns. Cycle_Offset is incremented every 40 ns.
3.4.6
Diagnostics Register at 18h
This register defaults to 4000 0000h and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
Reserved
N/A
Reserved
1
AckTardy
R/W
Ack_tardy response enable. When this bit is set to 1, an Ack_tardy response is sent. When set to 0, an
Ack_busy response is sent. This bit defaults to 1.
2
BudgEn
R/W
Budget counter enable. When this bit is set to 1, the internal budget counter is enabled.
3
Reserved
N/A
Reserved
4
RegRW
R/W
Register read/write access. Note: RegRW is used in the test mode and must not be set during normal
operations.
5
AgntStWr
R/W
Agent write access. When AgntStWr is set to 1, agent state is read/write. When this bit is set to 0, the agent
state is not accessible.
6
Reserved
N/A
Reserved
7
AgRdy0
R/O
Agent0 ready. This bit indicates whether Agent0 has been assigned a node ID and is valid. When AgRdy0
is set to 1, command block agent 0 is ready to be written or read. When AgRdy0 is set to 0, command block
agent 0 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
8
AgRdy1
R/O
Agent1 ready. This bit indicates whether Agent1 has been assigned a node ID and is valid. When AgRdy1
is set to 1, command block agent1 is ready to be written or read. When AgRdy1 is set to 0, command block
agent1 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
9
AgRdy2
R/O
Agent2 ready. This bit indicates whether Agent2 has been assigned a node ID and is valid. When AgRdy2
is set to 1, command block agent2 is ready to be written or read. When AgRdy2 is set to 0, command block
agent2 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
10
AgRdy3
R/O
Agent3 ready. This bit indicates whether Agent3 has been assigned a node ID and is valid. When AgRdy3
is set to 1, command block agent3 is ready to be written or read. When AgRdy3 is set to 0, command block
agent3 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
1113
Reserved
N/A
Reserved
14
MAAckconf
R/W
Management agent ack_conflict. When this bit is set to 1, ack_conflict response is transmitted when the
management agent is busy. This bit is the same as MAAckConf at 08h bit 19.
1517
Reserved
N/A
Reserved
1823
Budget_Counter
R/O
Budget counter value. This field specifies the current value of the internal budget counter.
2431
Reserved
N/A
Reserved
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