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參數(shù)資料
| 型號(hào)： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁數(shù)： | 80/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
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313
3.4.12 ARF Status Register at 30h
This register defaults to 1000 008Eh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
ARFFul
R/O
ARF full flag. When the ARF is full, ARFFul is set to 1 and writes are ignored. Otherwise, ARFFul is set to 0.
This bit defaults to 0 and is set to 0 on a bus reset.
1
ARFAFl
R/O
ARF almost-full flag. While the ARF can accept at least one more quadlet, ARFAFl is set to 1. Otherwise
ARFAFl is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
2
ARFAEm
R/O
ARF almost-empty flag. While the ARF contains only one quadlet, ARFAEm is set to 1. Otherwise
ARFAEm is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
3
ARFEmp
R/O
ARF empty flag. When the ARF is empty, ARFEmp is set to 1. Otherwise, ARFEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
46
Reserved
N/A
Reserved
715
ARFThere
R/O
ARF there. The number of quadlets received in the ARF. This field defaults to 0 and is set to 0 on a bus
reset.
16
ARFCD
R/O
ARF control bit. When the first quadlet of a packet is read from the ARF data (80h) register, ARFCD is set to
1. This bit defaults to 0 and is set to 0 on a bus reset.
1718
Reserved
N/A
Reserved
19
ARFClr
S/C
ARF clear control bit. When ARFClr is 1, the ARF is cleared of all entries. This bit is cleared after the ARF is
cleared. This bit defaults to 0 and is cleared on a bus reset.
2022
Reserved
N/A
Reserved
2331
ARF_Size
R/W
ARF_Size control bits. Size is equal to the ARF size number in quadlets. This field defaults to 8Eh and is
unaffected by a bus reset.
3.4.13 MTQ Status Register at 34h
This register defaults to 1000 0000h and, except for the bits specified, is cleared on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
MTQFul
R/O
MTQ full flag. When the MTQ is full, MTQFul is set to 1 and writes are ignored. Otherwise, MTQful is set to
0. This bit defaults to 0 and is set to 0 on a bus reset.
1
MTQAFl
R/O
MTQ almost-full flag. While the MTQ can accept only one more quadlet write, MTQAFl is 1. Otherwise,
MTQAFl is set to 0. Note: This bit is set after 3 quadlets are written. This bit defaults to 0 and is set to 0 on a
bus reset.
2
MTQAEmp
R/O
MTQ almost-empty flag. While the MTQ contains only one quadlet, MTQAEmp is set to 1. Otherwise,
MTQAEmp is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
3
MTQEmp
R/O
MTQ empty flag. When the MTQ is empty, MTQEmp is set to 1. Otherwise, MTQEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
418
Reserved
N/A
Reserved
19
MTQClr
S/C
MTQ clear control bit. When MTQClr is set to 1, the MTQ is cleared. This bit is cleared after the MTQ is
cleared. This bit defaults to 0 and is cleared on a bus reset.
2031
Reserved
N/A
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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