- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄199479 > TSB43AA82GGW (TEXAS INSTRUMENTS INC) 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 PDF資料下載
參數(shù)資料
| 型號(hào)： | TSB43AA82GGW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封裝： | PLASTIC, BGA-176 |
| 文件頁(yè)數(shù)： | 76/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82GGW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)當(dāng)前第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)
39
3.4.4
Interrupt/Interrupt Mask Registers at 0Ch/10h
The interrupt and interrupt mask registers work in tandem to inform the host bus interface when the state of the
TSB43AA82 changes. The interrupt is at address 0Ch and the interrupt mask is at address 10h. The interrupt register
defaults to 0000 0000h and is unaffected by a bus reset. The interrupt mask register defaults to 8000 0000h and is
unaffected by a bus reset. Each bit of the interrupt register represents a unique interrupt. A particular interrupt can
be masked off when the corresponding bit in the interrupt mask register is 0. The interrupt register shows the status
of the individual bits even when the interrupt is masked off.
BITS
ACRONYM
DIR
DESCRIPTION
0
Int
R/O
Interrupt. Int contains the value of all interrupt bits and interrupt mask bits logically ORed together. The
inverse of this bit is connected to the XINT bit (terminal 54, U9). When the logically ORed value of all
interrupt and mask bits is 1, Int is set to 1. When the logical ORed value of all interrupt and mask bits is 0, Int
is set to 0.
1
PhInt
S/C
PHY chip interrupt. When the PHY layer signals an interrupt to the internal link chip, PhInt is set to 1.
2
Breset
S/C
Bus reset. When the internal PHY initializes or detects a bus reset, Breset is set to 1.
3
CmdSlf
S/C
Command reset packet received. CmdSlf is set to 1 when the receiver (TSB43AA82) is sent a quadlet
write request addressed to the RESET_START (FFFF F000 000Ch) CSR register. The command reset
packets are stored in the ARF.
4
Endslf
S/C
End of the self-ID process. When the link layer detects the end of self-ID process, Endslf is set to 1.
5
Phypkt
S/C
PHY packet detect. When the receiver receives a PHY packet, Phypkt is set to 1.
6-7
Reserved
N/A
Reserved
8
SntRj
S/C
Busy acknowledge sent by receiver. When the TSB43AA82 is forced to send an ack_busy_X to an
incoming packet because the receive FIFO overflowed, SntRj is set to 1.
9
PhRRx
S/C
PHY register information received. When a PHY register value is transferred to the Phy_Access register
from the PHY interface, PhRRx is set to 1.
10
IFAcc
S/C
Invalid FIFO access. When IFAcc is set to 1, the ATF access sequence is violated.
11
HdrErr
S/C
Header error. When the receiver detects a header CRC error on an incoming packet that may have been
addressed to this node, HdrErr is set to 1.
12
TCErr
S/C
tCode error. When the transmitter detects an invalid tCode in the data, TCErr is set to 1.
13
CySec
S/C
Cycle second. When the Seconds_Count field in the cycle-timer register (14h) is incremented, CySec is
set to 1.
14
Cyst
S/C
Cycle started. When the transmitter sends or the receiver receives a cycle-start packet, Cyst is set to 1.
15
Reserved
N/A
Reserved
16
DRHUpdate
S/C
DRF header update. When the host reads the packet header of DRF data, this bit is set to 1. This bit has no
meaning if DRHStr (90h) is set.
17
FaGap
S/C
Fair gap. When the serial bus has been idle for an arbitration reset gap, FaGap is set to 1.
18
TxRdy
S/C
Transmitter ready. When the transmitter is idle and ready, TxRdy is set to 1.
19
CyDne
S/C
Cycle done. When an arbitration gap is detected on the bus after the transmission or reception of a
cycle-start packet, CyDne is set to 1.
20
CyPnd
S/C
Cycle pending. When CyPnd is set to 1, the cycle timer offset is set to 0 (rolled over or reset) and remains
set until the isochronous cycle ends.
21
CyLst
S/C
Cycle lost. When the cycle timer rolls over twice without the reception of a cycle-start packet, CyLst is set to
1.
22
CyArbF
S/C
Cycle arbitration failed. When the arbitration to send the cycle-start packet fails, CyArbF is set to 1.
23
Reserved
N/A
Reserved
24
ATFEnd
S/C
ATF transaction end. When the transmitter completes transmission (received ack_comp, response
packet, timeout), ATFEnd is set to 1. The host can read the completion status from the transaction timer
control (60h) and the transaction timer status (64h6Ch) registers until the next process begins. This bit is
set to 1 when the response to a request packet sent by the ATF is received in the ARF. When an
independent request packet is received in the ARF, the ARFRxd bit is set.
25
ARFRxd
S/C
ARF received data. When the receiver confirms a request packet was received in the ARF, ARFRxd is set
to 1. This bit is not set for a received response packet.
26
MOREnd
S/C
Management ORB fetch completed. When the fetched management ORB is stored in the MRF, MOREnd
is set to 1. The host can read the completion status from transaction timer control (60h) and transaction
timer status (64h6Ch) registers until the next transaction begins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB43DA42GHCR | PCI BUS CONTROLLER, PBGA196 |
| TSB500SK02 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB500SK10MDS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000331DS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000831 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成電路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。