參數(shù)資料
型號(hào)： TMX320DM642GNZ500
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 75.19 MHz, OTHER DSP, PBGA548
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-548
文件頁(yè)數(shù)： 170/181頁(yè)
文件大?。?/td> 2291K
代理商： TMX320DM642GNZ500
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)當(dāng)前第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)
Terminal Functions
89
July 2002 Revised March 2004
SPRS200E
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPD/
IPU
TYPE
NAME
DESCRIPTION
IPD/
IPU
TYPE
NO.
ETHERNET MAC (EMAC)
HD31/AD31/MRCLK§
G1
I
EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive.
MII transmit clock (MTCLK),
HD30/AD30/MCRS§
H3
I
EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive.
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
HD29/AD29/MRXER§
G2
I
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
HD28/AD28/MRXDV§
J4
I
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
HD27/AD27/MRXD3§
H2
I
MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]).
HD26/AD26/MRXD2§
J3
I
This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]).
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network collision.
HD25/AD25/MRXD1§
J1
I
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network collision.
During full-duplex operation, transmission of new frames will not begin if this pin is
HD24/AD24/MRXD0§
K4
I
During full-duplex operation, transmission of new frames will not begin if this pin is
asserted.
MII carrier sense (MCRS)
HD22/AD22/MTCLK§
L4
I
asserted.
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
HD21/AD21/MCOL§
K2
I
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
HD20/AD20/MTXEN§
L3
O/Z
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
HD19/AD19/MTXD3§
L2
O/Z
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
HD18/AD18/MTXD2§
M4
O/Z
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]).
HD17/AD17/MTXD1§
M2
O/Z
This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]).
and MII receive error (MRXER),
HD16/AD16/MTXD0§
M3
O/Z
and MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL
VP0D[19]/AHCLKX0§
AC12
I/O/Z
IPD
VP0 input/output data 19 pin (I/O/Z) or McASP0 transmit high-frequency
master clock (I/O/Z).
VP0D[18]/AFSX0§
AD12
I/O/Z
IPD
VP0 input/output data 18 pin (I/O/Z) or McASP0 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
VP0D[17]/ACLKX0§
AB13
I/O/Z
IPD
VP0 input/output data 17 pin (I/O/Z) or McASP0 transmit bit clock (I/O/Z).
VP0D[16]/AMUTE0§
AC13
O/Z
IPD
VP0 input/output data 16 pin (I/O/Z) or McASP0 mute output (O/Z).
VP0D[15]/AMUTEIN0§
AD13
I/O/Z
IPD
VP0 input/output data 15 pin (I/O/Z) or McASP0 mute input (I/O/Z).
VP0D[14]/AHCLKR0§
AB14
I/O/Z
IPD
VP0 input/output data 14 pin (I/O/Z) or McASP0 receive high-frequency master clock
(I/O/Z).
VP0D[13]/AFSR0§
AC14
I/O/Z
IPD
VP0 input/output data 13 pin (I/O/Z) or McASP0 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
VP0D[12]/ACLKR0§
AD14
I/O/Z
IPD
VP0 input/output data 12 pin (I/O/Z) or McASP0 receive bit clock (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA
VP1D[19]/AXR0[7]§
AB12
VP1D[18]/AXR0[6]§
AB11
VP1D[17]/AXR0[5]§
AC11
VP1D[16]/AXR0[4]§
AD11
I/O/Z
IPD
VP0 input/output data pins [19:12] (I/O/Z) or McASP0 TX/RX data pins [7:0] (I/O/Z).
VP1D[15]/AXR0[3]§
AE11
I/O/Z
IPD
VP0 input/output data pins [19:12] (I/O/Z) or McASP0 TX/RX data pins [7:0] (I/O/Z).
VP1D[14]/AXR0[2]§
AC10
VP1D[13]/AXR0[1]§
AD10
VP1D[12]/AXR0[0]§
AC9
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
ADV
ANCE
INFORMA
TION
相關(guān)PDF資料
PDF描述
TN4002PM 10 MHz - 500 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER
TN5171PM 20 MHz - 150 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER
TOCP172-1MB 970/1000 um, MULTI MODE, SIMPLEX FIBER OPTIC CONNECTOR
TOCP172-20CB 970/1000 um, MULTI MODE, SIMPLEX FIBER OPTIC CONNECTOR
TOD5202FE Optoelectronic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320DM6435AZDU 制造商:Texas Instruments 功能描述:
TMX320DM6437AZDUA 功能描述:開(kāi)發(fā)板和工具包 - TMS320 Digl Media Processor RoHS:否 制造商:Texas Instruments 產(chǎn)品:Experimenter Kits 工具用于評(píng)估:F2802x 核心:TMS320 接口類型:UART, USB 工作電源電壓:
TMX320DM6437AZWTA 制造商:Texas Instruments 功能描述:TMX320DM6437 PG1.1 361PIN PB-FREE NFBGA - Trays
TMX320DM6437BZDUA 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Media Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMX320DM6437BZWTA 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Media Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*