參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁數(shù): 90/120頁
文件大?。?/td> 1542K
代理商: TMUX03155
90
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 76. Register 127: Page Control Register (R/W)
Table 77. Page 0 - Registers 128—191: J1 Insert Parameters (R/W)
Table 78. Page 0 - Registers 192—255: J1 Monitor Bytes (RO)
Table 79. Page 1 - Registers 128—133: STS-1/AU-3 B1 BIP Error Counters (RO)
Address
Dec (Hex)
127 (0x7F)
Bit
Name
Function
Reset
Default
00
1—0
PAGE[1:0]
Page Number.
Control bits select the page
accessed when an address greater than 128 is
accessed: 00 = Page 0 (J1 Byte Insert/Monitor),
01 = Page 1 (Error Counters), 10 = Page 2 (BER
Algorithm Parameters), 11 = Illegal Value.
Address
Dec (Hex)
128 (0x80)—
191 (0xBF)
Bit
Name
Function
Reset
Default
0x00
7—0
TJ1DINS[64—1][7:0]
Transmit J1 Data Insert.
Registers allow a
64-byte sequence to be inserted into the J1 byte
of the STM-1(AU-4) output signal.
Address
Dec (Hex)
Bit
Name
Function
Reset
Default
0x00
192 (0xC0)—
255 (0xFF)
7—0
RJ1MON[64—1][7:0]
Receive J1 Monitor Data.
Registers capture a
64-byte sequence from the selected
(J1PSELMON[1:0], 0x56) J1 byte of the STS-3/
STM-1 (AU-4) input signal.
Address
Dec (Hex)
128 (0x80)—
133 (0x85)
Bit
Name
Function
Reset
Default
0x0000
7—0
TLSB1ECNT[1—3][15:8]
TLSB1ECNT[1—3][7:0]
Transmit Low-Speed B1 Error Count.
These
are the B1 BIP error rate counters. These
counters can either count actual BIP errors or
block errors (BITBLOCKCNT, 0x34). These
counters hold at their maximum values and trans-
fer their internal counts to a holding register when
LATCH_CNT, 0x04 transitions from a logic 0 to 1.
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