參數(shù)資料
型號(hào)： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 82/120頁
文件大小： 1542K
代理商： TMUX03155
82
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 60. Register 86: Receive J1 and Receive Low-Speed Port Select Control (R/W)
Table 61. Register 87: STS-1/AU-3 Receive Control Bits (R/W)
Address
Dec (Hex)
86 (0x56)
Bit
Name
Function
Reset
Default
00
7—6
J1PSELMON[1:0]
J1 Port Select Monitor Control.
Control bits are
used to select which J1 byte will be monitored in the
received STS-3/STM-1 (AU-4) signal: 00 = port 1,
01 = port 2, 10 = port 3, 11 = undefined operation.
Receive Port Select Control.
Control bits allow
receive output selection: 00 or 11 = port 1 selected,
01 = port 2 selected, 10 = port 3 selected.
86 (0x56)
5—4
3—2
1—0
RSEL[3—1][1:0]
10
01
00
Address
Dec (Hex)
87 (0x57)
Bit
Name
Function
Reset
Default
000
7—5
RLSSCR[3—1]
Receive Low-Speed Scrambler Enable.
Control
bit, when set to a logic 1, causes the selected
STS-1/AU-3 output signal to be scrambled; other-
wise, the output signal is not scrambled.
Receive High-Speed Port or CDR Clock and
Data Select.
Control bit, when set to a logic 0,
causes the differential receive clock and data inputs
(RHSSCLKIT/C, RHSSDATAIT/C) to be used in the
device receive path; otherwise, the outputs of the
CDR clock recovery block are used.
Path AIS or LOP AIS Inhibit.
Control bit, when set
to a logic 0, causes state bits PAIS and LOP to con-
tribute to the generation of Path AIS; otherwise, the
state bits are inhibited from contributing to Path AIS
generation.
Transmit Low-Speed to Receive Low-Speed
Loopback.
Control bit, when set to a logic 1,
causes the transmit STS-1/AU-3 input signals to be
looped back to the receive STS-1/AU-3 outputs;
otherwise, loopback is disabled.
Receive Low-Speed Clock Invert Control.
Con-
trol bit, when set to a logic 1, causes the output
clock to be inverted; otherwise, the output STS-1/
AU-3 receive clock is not inverted.
Receive Low-Speed Parity Odd or Even Genera-
tion.
Control bit, when set to a logic 1, forces the
output parity bit to be even; otherwise, the parity is
odd.
87 (0x57)
4
RHSPorCDRSEL
0
87 (0x57)
3
PAISLOP_AISINH
0
87 (0x57)
2
TLS2RLSLB
0
87 (0x57)
1
RLSCLKINV
0
87 (0x57)
0
RLSPAROEG
0
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