參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 71/120頁
文件大小： 1542K
代理商： TMUX03155
Agere Systems Inc.
71
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 48. Register 73: Tandem Connection Byte (R/W)
Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W)
Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W)
Address
Dec (Hex)
73 (0x49)
Bit
Name
Function
Reset
Default
0x00
7—0
TZ5DINS[7:0]
Transmit Z5 Data Insert Value.
Register value is
inserted into the STM-1(AU-4) output Z5 byte.
Address
Dec (Hex)
74 (0x4A)
Bit
Name
Function
Reset
Default
1
7
TLRDIINH
Transmit RDI-L Inhibit Control.
Control bit, when
set to a logic 0, allows software to insert the
TK2INS[2:0] byte, 0x43 into the outgoing K2[2:0]
bits; otherwise, Line RDI 110 is inserted if the
appropriate alarms are active.
Transmit Receive High-Speed Signal Fail L-RDI
Inhibit.
Control bits, when set to a logic 1, causes
the associated failure not to contribute to the auto-
matic insertion of RDI-L; otherwise, the associated
alarm contributes to the generation of RDI-L.
TRLAISMON_LRDIINH
Transmit Receive Line AIS Path RDI Inhibit.
Same as above.
TRHSLOF_LRDIINH
Transmit Receive High-Speed Loss-of-Frame
Line RDI Inhibit.
Same as above.
TRHSOOF_LRDIINH
Transmit Receive High-Speed Out-of-Frame
Line RDI Inhibit.
Same as above.
TRHSLOS_LRDIINH
Transmit Receive High-Speed Loss-of-Signal
Line RDI Inhibit.
Same as above.
TRILOC_LRDIINH
Transmit Receive Input Loss-of-Clock Line RDI
Inhibit.
Same as above.
74 (0x4A)
5
TRHSSF_LRDIINH
0
74 (0x4A)
4
0
74 (0x4A)
3
1
74 (0x4A)
2
0
74 (0x4A)
1
0
74 (0x4A)
0
0
Address
Dec (Hex)
75 (0x4B)
Bit
Name
Function
Reset
Default
0
7
TPRDIINS
Transmit RDI-P Insert.
Control bit, when set to a
logic 1, allows software to insert P-RDI into the out-
going G1[3] bit, AU-4 mode only; otherwise, insert
Path RDI under hardware control.
Transmit Receive Loss-of-Pointer Path RDI
Inhibit.
Control bits, when set to a logic 1, causes
the associated failure not to contribute to the auto-
matic insertion of RDI-P; otherwise, the associated
alarm contributes to the generation of RDI-P
(port 1, AU-4 mode only).
Transmit Receive Path AIS Path RDI Inhibit.
Same as above.
75 (0x4B)
6
TRLOP1_PRDIINH
0
75 (0x4B)
5
TRPAIS1_PRDIINH
0
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