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參數(shù)資料
| 型號(hào)： | TMUX03155 |
| 英文描述： | TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer |
| 中文描述： | TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 29/120頁 |
| 文件大?。?/td> | 1542K |
| 代理商： | TMUX03155 |
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Agere Systems Inc.
29
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions
(continued)
Common Maintenance and Control Functions
(continued)
Device Version and Device ID Number
The device will have a version number (
DEVVER[7:0], 0x03
). The version increments each time the device func-
tionality is changed, from the controller’s perspective. The device ID (
DEVID[15:0], 0x01—0x02
) is a fixed pattern
used to identify the device by software.
Scratch Byte
The device will provide a 1-byte scratch register for the control interface to verify write capability to the device
(
SCRATCH[7:0], 0x06
).
Multibyte Registers
If a read value parameter register requires more than 8 bits, the device must prevent the value from changing
between 8-bit read commands. In these cases, the controller reads the lowest
address byte first and transfers the
higher address bytes to a holding register where the value is held until the controller reads them. Similarly, if a
multibyte writable register is implemented, the controller writes the lowest address byte first, which is stored in a
holding register until the controller writes the highest address byte, and then all of the bytes take effect.
To simplify device design, the controller reads or writes all of the bytes of a multibyte register before reading or writ-
ing other registers so that the holding registers may be shared among all multibyte registers. This read/write oper-
ation is valid on all multibyte registers not controlled by the
LATCH_CNT, 0x04
bit.
Update Counter Control
For performance monitoring purposes, there are a number of BIP, FEBE, and pointer interpreter increment/decre-
ment error counters in the receive/transmit section. All of these internal counters are comprised of a running error
counter and a hold register that present stable results to the microprocessor. The counts in all of the running
counters are latched to the hold registers when
LATCH_CNT, 0x04
is written from a logic 0 to a logic 1. This zeros
all of the running counters. The results are held to be read by the microprocessor. All of the internal counters have
the ability to store more than 1 second’s worth of counts, so as long as the
LATCH_CNT
occurs every second, or
faster, no counts will be lost. In case this doesn’t happen, all of the running counters will hold their maximum value
rather than roll over to 0. The following counters
1
are affected by
LATCH_CNT
:
I
TLSB1ECNT[3—1][15:0], 0x08—0x85
I
TLSB2ECNT[1][17:0], 0x86—0x88
I
TLSB2ECNT[3—2][15:0], 0x89—0x8C
I
RHSB1ECNT[15:0], 0x8D—0x8E
I
RHSB2ECNT[17:0], 0x8F—0x91
I
RHSB3ECNT[3—1][15:0], 0x92—0x97
I
RPTR_INC[3—1[10:0], 0x98—0x9D
I
RPTR_DEC[3—1][10:0], 0x9E—0xA3
I
RSFEBECNT[17:0], 0xA4—0xA6
I
RPFEBECNT[3—1][15:0], 0xA7—0xAC
1 All addresses for these counters are in Page 1 registers.
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