參數(shù)資料
型號(hào)： TMPR4956F
廠(chǎng)商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 32/60頁(yè)
文件大小： 244K
代理商： TMPR4956F
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
32
Figure 7-6 Processor non-coherent block request protocol
5.7.6
External request protocol
External requests can only be issued when the system interface is in the slave state. The external agent
asserts the ExtRqst* signal, and requests use of the system interface. The processor asserts the Release*
signal, releases the system interface, waits for it to enter the slave state, then the external agent issues an
external request. If the system interface is already in the slave mode, namely, if the processor has put the
system interface in the slave state on its own, then the external agent can immediately issue an external
request.
In the case of the external agent, the system interface must be returned to the master state after issuing an
external request. When the external agent issues a single external request, ExtRqst* must be deasserted 2
cycles after the cycle at which Release* is asserted. Also, when issuing a series of external requests, the
ExtRqst* signal must be asserted before the last request cycle.
The processor continues processing external requests while ExtRqst* is asserted. However, until the
processor completes a request that is currently being processed, it will not be able to release the system
interface and put it into the slave state in preparation for the next external request. Also, until ExtRqst* is
asserted, a series of external requests cannot be interrupted by a processor request. This protocol is the
same for both the 64-bit and 32-bit bus modes.
Master
6
Master
Clock
SysAD bus
Cycle
SysCmd bus
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
1
2
3
4
5
7
8
9
10
11
12
Addr
Data0
Data1
Data2
Data3
Write
NData
NData NData
NEOD
1
2
5
4
3
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