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| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 24/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
24
State of the replaced data cache line
Dirty (W = 0)/Invalid
NCR
Page Properties
Dirty (W = 1)
NCR/W
Non-coherent
NCR:
NCR/W:
Processor non-coherent, block read request
Processor non-coherent, block write requests continue after the block read request
Table 6-1 Load Miss to the Primary Cache
5.6.2
Store miss
When a store miss occurs in the primary cache, the processor cannot proceed to the next process if it does
not receive from the external agent a cache line that includes a store target address. The processor checks
the coherency properties in the TLB entries for pages including the requested cache line, then confirms
whether to invalidate write transactions to that cache line or not.
After that, the processor executes one of the following requests:
If the coherency properties are non-coherent write back or non-coherent write through (write
allocate), then a non-coherent block read request is issued.
If the coherency properties are non-coherent write through (non-write allocate), then a non-block
write request is issued. Table 6-2 indicates the measures taken when there is a store miss to the
primary cache.
State of the replaced data cache line
Dirty (W = 0)/Invalid
NCR
Page Properties
Dirty (W = 1)
NCR/W
Non-coherent write back or
non-coherent write through (write
allocate)
Non-coherent write through
(non-write allocate)
NCW
NA
NCR:
NCR/W:
NCW:
Processor non-coherent, block read request
Processor non-coherent, block write requests continue after the block read request
Processor non-coherent write request
Table 6-2 Store Miss to Primary Cache
5.6.3 Store hits
Operation in the system interface is determined by whether a line is write back or write through. When in
the primary cache mode, all lines set to write back are set to the dirty exclusion state (W = 1). In other
words, burst transactions do not occur even if a store hit occurs. Lines set to write through generate
processor write requests for store data.
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