參數(shù)資料
型號(hào)： TMPR4956F
廠商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 22/60頁(yè)
文件大小： 244K
代理商： TMPR4956F
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
22
After the external request is issued, the system interface access privileges always return to the processor.
The processor will not accept another external request until the current one is complete.
If there is no processor request that is on hold, the processor decides based on the interior state whether to
accept an external request or to issue a new processor request. The processor can issue a new processor
request even if the external agent requested access to the system interface.
The external agent sends notification that it would like to start an external request by asserting the
ExtRqst* signal. After that, the external agent waits for the processor to assert the Release* signal and
send notification that preparations have been made to accept this request. The processor sends
notification based on the next judgement criterion to be listed that preparations have been made to accept
an external request.
The processor ends processor requests that are in progress.
The processor can accept an external request while waiting for the RdRdy* signal to be asserted
so a processor read request can be issued. However, this request must be transferred to the
processor at least 1 cycle before the RdRdy* signal is asserted.
The processor can accept an external request while waiting for the WrRdy* signal to be asserted
so a processor write request can be issued. However, this request must be transferred to the
processor at least 1 cycle before the WrRdy* signal is asserted.
If waiting for a response to a read request after the processor shifted itself to the slave state, the
external agent can issue an external request before sending read response data.
5.5.6 External read requests
In contrast to processor read requests, data are directly returned as a response to the request for external
read requests. No other requests can be issued until the processor returns the requested data. External
read requests are complete when the processor returns the requested data word. Depending on the data
identifier combined with the response data, an error in the response data may be pointed out. The
processor would process the error as a bus error.
Note:
The TX4956 does not have any resources that can read external read requests. The processor
returns to the external read request undefined data and data identifiers in which SysCmd(5) of the
errant data bit is set.
5.5.7
External write requests
When the external agent issues a write request, the specified resources are accessed, then the data are
written to those resources. External requests are complete when the data word is transferred to the
processor.
The only processor resource that an external write request can use are the Interrupt registers.
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