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| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 23/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
23
5.5.8
Read responses
As illustrated in Figure 5-7, read responses return data to processor read requests. Read responses are
external requests, strictly speaking, but there is only one difference with other external requests: read
responses do not request permission to use the system interface. Therefore, read responses are handled
separately from other external requests and are simply referred to as read responses.
Figure 5-7 Read Response
5.6
Handling of Requests
This section will describe in detail sequences, protocol, and syntax for both processor and external
requests.
Load miss
Store miss
Store bit
Cache operation
Load Linked/Store Conditional
5.6.1 Load miss
If a processor load miss occurs in the primary cache, the processor cannot proceed to the next process if
the cache line that contains the loaded data elements is not received from the external agent.
If the current cache line set in which the write back bit (W bit) is set is replaced by a new cache line, the
current cache line must be written back.
The processor checks the coherency properties in the TLB entries for pages including the requested cache
lines. If the coherency properties are non-coherent, then a non-coherent read request is issued. Table 6-1
indicates the measures that can be taken when a load miss occurs in the primary cache.
1. Read request
TX4956
External agent
2. Read response
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