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參數(shù)資料
| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 15/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
15
5.4
System Interface Protocol
Figure 4-1 illustrates the system interface that operates between registers. In other words, processor
output is directly transferred from the output register and changes and the Master Clock rising edge.
Processor input is directly transferred to the input register and the input register latches these input signals
at the rising edge of the Master Clock. In this way, it becomes possible for the system interface to operate
at the fastest clock frequency.
Figure 4-1 Operation of the System Interface Between Registers
5.4.1 Master state and slave state
The system interface is placed in the master state when the TX4956 processor is driving the SysAD bus
and SysCmd bus. In contrast, the system interface is in the slave state when the external agent is driving
the SysAD bus and SysCmd bus.
The processor asserts the ValidOut* signal if the SysAD bus and SysCmd bus become valid when the
system interface is in the master state. The external agent asserts the ValidIn* signal if the SysAD bus
and SysCmd bus become valid when the system interface is in the slave state.
5.4.2 Shifting from the master state to the slave state
The system interface remains in the master state unless it enters one of the following states:
The external agent issues a request, then usage of the system interface is granted (external
arbitration).
The processor issues a read request and shifts into the slave mode by itself.
5.4.3 External arbitration
The external agent cannot issue external requests via the system interface unless the system interface goes
Master Clock
TX4956
Output data
Input data
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