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參數(shù)資料
| 型號(hào)： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計(jì)算機(jī)）微處理器（64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 13/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
13
5.3.3 Issue cycle
Two types of processor issue cycles exist with the TX4956.
Processor read request issue cycles.
Processor write request issue cycles.
The TX4956 judges the issue cycle of the processor read request by sampling the RdRdy* signal. It also
judges the issue cycle of the processor write request by sampling the WrRdy* signal from the external
agent.
As illustrated in Figure 3-2, RdRdy* must be asserted two cycles before the processor read request
address cycle in order to define the address cycle as an issue cycle.
Figure 3-2 RdRdy* Signal Status in case of Read Request
As illustrated in Figure 3-3, WrRdy* is asserted two cycles before the initial address cycle of the
processor write request, and the address cycle must be defined as the issue cycle.
Figure 3-3 WrRdy* Signal Status in case of Write Request
Address
2
3
4
5
6
1
Issue
Cycle
Cycle
Master Clock
SysAD Bus
RdRdy*
ValidOut*
1
2
3
4
5
6
Address
Data
Cycle
Master Clock
SysAD
Bus
WrRdy*
ValidOut
*
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