參數(shù)資料
型號(hào)： TMPR4956F
廠商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 28/60頁(yè)
文件大?。?/td> 244K
代理商： TMPR4956F
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
28
5.7.3
Processor write request protocols
Either of the two following protocols is used in issuing processor write requests.
The word write request protocol (see Note below) is used for double word, partial double word,
word or partial word writing.
Note:
Words are called to differentiate from the block request protocol. It is actually
possible to transfer data in double word, partial double word, word, or partial word units.
The block write request protocol is used for block write transactions.
The system interface is used in the master state to issue processor double word write requests. Figure 7-2
illustrates processor non-coherent single word write request cycles.
1.
In order to issue a processor single word write request, a write command is sent to the SysCmd bus,
and a write address is sent to the SysAD bus.
2.
The processor asserts the ValidOut* signal.
3.
The processor sends the data identifier to the SysCmd bus and transmits data to the SysAD bus.
4.
The data identifier for this data cycle must receive an indication that this is the final data cycle.
ValidOut* is deasserted at the end of the cycle.
Note:
The SysADC bus and SysCmd bus timing is the same as the SysAD bus and SysCmd bus,
respectively.
Figure 7-2 Processor Non-coherent Single Word Write Request Protocol
5.7.4
Processor single write requests
There are three processor single write requests as follow below.
Master
6
Master
Clock
Cycle
SysAD bus
SysCmd bus
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
1
2
4
5
7
8
9
3
11
12
10
Addr
Data0
Write NEOD
1
3
2
4
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