參數(shù)資料
型號(hào)： TK68HC24
廠商： Electronic Theatre Controls, Inc.
英文描述： Port Replacement Unit (PRU)
中文描述： 港口更換單元（普天壽）
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 98K
代理商： TK68HC24
Tekmos
TK68HC24 PRU
9
www.Tekmos.com
8/21/99
I/O Port Operation
There are two 8-bit parallel I/O ports on the
TK68HC24. Port B is a general purpose output-
only port. Port C may be used as general purpose
input and/or output pins, as specified by the DDRC
register. In conjunction with STRA and STRB, ports
B and C may be used for special strobed and
handshake modes of parallel I/O as well as general
I/O.
Fixed Direction I/O (Port B)
Port B is a general purpose output-only port. The
data direction is fixed in order to properly emulate
the operation of the 68HC11 Port B. Reads of Port
B return the levels sensed at the input of the pin
drivers. Write data is stored in an internal latch
which directly drives the output pin driver. Reset
clears the data register, forcing the outputs low.
General Purpose I/O (Port C)
When used as a general purpose I/O port, each pin
has associated with it one bit in the Port C data
register and one bit in the corresponding position in
the data direction register (DDRC). The DDRC is
used to specify the primary direction of data on the
I/O pin. However, specification of a line as an
output does not disable the ability to read the line
as a latched input.
When a bit which is configured as an output is read,
the value returned will be the value at the input to
the pin driver. When a pin is configured as an input
(by clearing the DDRC bit) then pin becomes a
high-impedance input. When writing to a bit that is
configured as an input, the value will not affect the
I/O pin. However, the bit will be stored in the
PORTC latch, and will drive the pin should the
DDRC register ever be set.
This operation can be used to preset a value for an
output port prior to configuring it as an output, so
that glitches of an output state which are not
defined for the external system may be avoided.
Reset configures the port for input by clearing both
the DDRC and PORTC registers.
Simple Strobed I/O
The simple strobed mode of parallel I/O is selected
when the HNDS bit in the PIOC (Parallel I/O
Control) register is clear. This mode forces
PORTCL to be a strobed input port with the
selected edge of the STRA pin used to latch the
data. Port B becomes a strobed output port with
the STRB pin acting as the output strobe.
Strobed Input Port C
Even in the input mode, the DDRC register still
controls the direction of the Port C pins. As a
result, if a bit in the DDRC register is set, that bit
still acts as an output from the Port C register.
Depending on the edge selected by the EGA bit in
the PIOC register, either the positive edge (EGA =
1) or the negative edge (EGA = 0) of the STRA
strobe will latch the values on the Port C pins into
the PORTCL register. The action will also set the
STAF bit in the PIOC register.
If the STAI bit in the PIOC register is also set, then
an interrupt sequence is requested in the IRQN pin.
The STAF flag is automatically cleared by reading
the PIOC register (with STAF set), followed by a
read of the PORTCL register. Additional active
edges of the STRA pin will continue to latch new
data into the PORTCL register, regardless of the
state of the STAF flag. Consecutive active edges of
the STRA signal must be a minimum of two E-clock
cycles apart.
Reads of the PORTCL register return the last value
latched. Reads of the PORTC register return either
the in value for inputs or the contents of the PORTC
register for outputs.
Strobed Output Port B
In this mode, the STRB pin is a strobe output which
is pulsed each time there is a write to Port B.
FULL HANDSHAKE I/O
The full handshake modes of parallel I/O use Port
C, the DDRC port, STRA, and STRB. There are
the two basic modes of input and output, and an
additional variation on the output handshake mode
that allows for three-state operation of Port C. In all
handshake modes, STRA is an edge detecting
input and STRB is a handshake output line.
Input Handshake Protocol
In the input handshake mode, Port C is a latching
input port, STRA is an edge-sensitive latch
command from the external system that is driving
Port C and STRB is a READY output line controlled
by logic in the TK68HC24.
In a typical system, an external device wishing to
write to Port C would test the READY line (STRB).
When a ready condition was recognized, the
external device would place data on the Port C
inputs and then pulse the STRA input to the
TK68HC24. The active edge on the STRA line
would latch the Port C data into the PORTCL
register, set the STAF flag (optionally causing an
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