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參數(shù)資料
| 型號(hào)： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁(yè)數(shù)： | 6/21頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | TK68HC24 |
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Tekmos
TK68HC24 PRU
6
www.Tekmos.com
8/21/99
drivers allowing wired-OR type external
connections. When CWOM equals one,
the top driver device is disabled so that pins
may be driven low by writing zeros or
become three-state by writing ones. With
an external pull-up resistor, the non-driven
lines are pulled to logic ones.
This permits Port C output pins to be safely
wired in parallel with similar CMOS output
drivers without fear of contentions which
could otherwise cause destructive latch-up.
This bit is cleared by RESET so Port C pins
which are configured as outputs will
operate normally.
Note that even when in the wired-or mode,
the input protection diodes are still there,
and so input voltages must never exceed
VDD.
HNDS
– Bit 4, Read / Write
When HNDS (handshake mode) bit is clear,
the STRA pin acts as a simple input strobe
to latch incoming data into the PORTCL
latch register and the STRB pin acts as a
simple output strobe that pulses after any
write to Port B. When HNDS is set, it
specifies that a handshake protocol
involving Port C, STRA, and STRB is in
effect. In all modes, STRA is an edge-
sensitive input and STRB is an output. This
bit is cleared by RESET. The strobe and
handshake modes are described in greater
detail in I/O PORTS.
OIN
– Bit 3, Read / Write
The OIN (output or input handshake) bit
has no meaning or effect unless HNDS is
set to one. When this bit is zero, input
handshake protocol is specified. When this
bit is a one, output handshake protocol is
specified. See I/O PORTS for a more
detailed description of the handshake
protocols.
PLS
– Bit 2, Read / Write
The PLS (pulse/interlocked handshake) bit
has no meaning or effect unless HNDS is
set to one. When this bit is zero,
interlocked handshake operation is
specified. When this bit is one, pulse mode
handshake operation is specified.
In interlocked modes, the STRB output line,
once activated, remains active indefinitely
until the selected edge is detected on the
STRA input line. In pulse modes, the
STRB output line, once activated, remains
active for only two MCU E-clock cycles and
then automatically reverts to the inactive
state. This bit is cleared by RESET. For
more details on the handshake protocols,
see I/O PORTS.
EGA
– Bit 1, Read / Write
The EGA (active edge for STRA) bit is used
to specify which edge (rising or falling) on
the STRA input pin is to be considered the
active edge. When this bit is zero, the
active edge is the falling edge and when
this bit is one, the active edge is the rising
edge. This bit is set to one by RESET.
When output handshake mode is specified,
this bit is used to control the PORTC three-
state variation as well as select the active
acknowledge edge. In the three-state
variation, the EGA bit specifies the trailing
edge polarity for the STRA input pin which
is interpreted as the enable/acknowledge
signal. Assertion of STRA overrides the
DDRC specifications to force Port C to be
outputs and the edge of negation is the
active edge acknowledge command.
If EGA is zero, the falling edge at STRA is
the active edge which causes STAF to be
set and STRB to be negated. Additionally,
if EGA is zero, Port C bits obey the DDRC
specification while STRA is low but Port C
is forced to be an output when STRA is
high.
If EGA is one, the rising edge of STRA is
the active edge. This causes STAF to be
set and STRB to be negated. In addition,
Port C bits obey the DDRC specification
while STRA is high, but Port C is forced to
be an output when STRA is low.
INVB
– Bit 0, Read / Write
The INVB (Invert Strobe B) bit is used to
specify whether or not to invert the normal
strobe B (STRB) logic output levels. When
this bit is one, no inversion is specified and
the active level on the strobe B output line
is logic one. When this bit is zero, inversion
is specified and the active level on the
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