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參數(shù)資料
| 型號(hào)： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁(yè)數(shù)： | 12/21頁(yè) |
| 文件大小： | 98K |
| 代理商： | TK68HC24 |
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Tekmos
TK68HC24 PRU
12
www.Tekmos.com
8/21/99
SYSTEM CONFIGURATION
The TK68HC24 allows an end user to configure the
peripheral to his specific MCU system through the
use of hard wired options such as the mode select
pin (MODE) and by the use of internal registers
under software control. The following section
describes those options which are fixed through
hardware. Other configuration options, which can
be changed dynamically, are discussed in the
sections entitled I
/O PORTS and MODES OF
OPERATION
.
MODE SELECTION
A dedicated mode select pin (MODE) determines
which of two operating modes the TK68HC24
enters out of RESET. Both modes properly emulate
the action of Ports B and C of the 68HC11. The
modes are the normal and special test modes.
The state of the mode select pin (MODE) is latched
into the peripheral by the rising edge of RESET with
the inverse of the latched value reflected in the
SMOD bit of the HPRIO register. Normal mode is
indicated by SMOD equals zero (MODE equals
one). Special Test mode is indicated by SMOD
equals one (MODE equals zero). The difference
between these two modes is limited to the operation
of the INIT and HPRIO registers.
The MODE input corresponds (in function, but not
voltage levels) to the MODB/VPGM input of the
68HC11. The 68HC11 requires either V
DD
or a
level 1.8 x V
DD
on the MODB pin to select the
operating mode; whereas, the TK68HC24 requires
only logic level signals. The 1.8 x V
DD
level
required by the 68HC11 corresponds to a logic low
on the TK68HC24. The V
DD
level required by the
68HC11 corresponds to a logic high on the
TK68HC24. In normal operation, the special test
mode is not used and the mode pin on both the
68HC11 and the TK68HC24 can be tied to V
DD
.
STATE AFTER RESET
When a low level is sensed on the RESET pin, the
TK68HC24 enters the reset state. Most of the
registers and control bits are forced to a specific
state during reset and, if a user requires a different
configuration, he must write the desired values into
these registers in his initialization software. For
detailed information about the options available,
see INTERNAL REGISTER DESCRIPTION.
Note that RESET is synchronized to the system
clock (E) before being used internally. For this
reason, RESET must be held low for a minimum of
two E-clock cycles to be recognized. Once
recognized, the peripheral is initialized as described
below.
Most of the configuration state after reset is
independent of the selected operating mode. The
STAF, STAI, and HNDS bits in the PIOC register
are initialized to zeros so that no interrupt is
pending or enabled and the simple strobed mode
(rather than full handshake modes) of parallel I/ O is
selected. The CWOM bit is initialized to zero (Port
C not operating in wire-OR mode). Port C is
initialized as a general purpose, high-impedance
input port (DDRC equals $00), STRA as an edge-
sensitive strobe input, and the active edge is initially
configured to detect rising edges (EGA bit set to
one by RESET). The STRB strobe output is initially
a zero (INVB bit is initialized to one), while Port B is
initialized with all outputs forced low.
The SMOD and IRV bits in the HPRIO register
reflect the status of the MODE input at the rising
edge of RESET. Reset also deselects the chip and
forces the multiplexed address/data bus to high
impedance inputs.
MODES OF OPERATION
SPECIAL TEST MODE
The special test mode is selected with MODE equal
to zero at the rising of edge of RESET. Initialization
into this mode loads HPRIO with $50 (SMOD and
IRV equal one) and disables the INIT register write-
protect mechanism.
While in special test mode (SMOD bit equals one),
the INIT register write-protect mechanism is
overridden and INIT remains writable as long as
SMOD remains one. When SMOD is written to a
zero (to enter the normal operating mode), the
write-protect mechanism is enabled. One additional
write is allowed after entering normal operating
mode regardless of the number of writes performed
while in the special test mode.
The reset state of IRV is one in the special test
mode. An attempted read of either the INIT or
HPRIO register with IRV equal to one will leave the
data bus in a high impedance state with the output
buffers disabled. If IRV equals zero, the data
buffers are enabled and the contents of the
selected register are placed on the data bus. The
IRV bit is writable only one time while in the special
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