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參數(shù)資料
| 型號： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 98K |
| 代理商： | TK68HC24 |
Tekmos
TK68HC24 PRU
2
www.Tekmos.com
8/21/99
Pinout
PDIP
40
1
2-5
6
7-14
PLCC
44
2
3-6
7
8-11,
13-16
17
18
19-22,
24-27
28
29
30-33,
35-38
39
40
41
42
43
44
Name
Type
Function
IOTEST
A15 – A12
STRA
PC0 – PC7
N / C
Input
Input
Bidirec
tional
Supply
Output
Output
Not used in the Tekmos design
Address lines for port mapping.
Handshake input
General purpose input / output port
15
16
17-24
VDD
STRB
PB7 – PB0
Positive supply
Handshake output
General purpose output port
25
26
27-34
IRQN
VSS
AD7 - AD0
Output
Supply
Bidirec
tional
Input
Input
Input
Input
Input
Input
Interrupt Request, open drain, active low
Ground
Multiplexed address / data bus from the 68HC11
35
36
37
38
39
40
RESETN
RWN
E
AS
MODE
CSN
Reset, active low
Read / Write control signal
Enable – clock
Address strobe
Selects operating mode at reset.
Chip select
Pin Descriptions
IOTEST
No Connect
The IOTEST pin was removed from the 68HC24
design several years ago. However, it continued to
be referenced on the data sheet. This pin is a true
no connect, and may be either tied to a convenient
supply, used for routing other signals, or it may be
left floating.
A15 – A12
High Order Address - Inputs
These are the high order address lines from the
processor. They are latched by the rising edge of
the E clock. The value on the address lines is
compared against the contents of the INIT register.
A match, combined with an active chip select
selects the part during the current bus cycle.
AD7 – AD0
Address and Data Bus - Bidirectional
These pins are a multiplexed address / data bus.
During the first portion of the bus cycle, when the E
clock is low, the AD bus contains the address. The
address is strobed into an internal address latch by
the ALE pin. During the second portion of the bus
cycle, when the E clock is high, the AD pins carry
data. Depending on the state of the RWN pin, the
part will either read the bus, or drive the bus.
STRA
Strobe A – Input
This pin is used as an input handshake signal by
Port C. In the simple strobed and input handshake
modes, STRA is used to latch data into the
PORTCL register. In the output handshake mode,
STRA is used to acknowledge the output data. The
EGA bit in the PIOC register controls which edge of
STRA is active.
STRB
Strobe B - Output
The STRB pin serves as an output strobe for Port B
when the part is operating in the simple strobed I/O
mode. In the handshake mode, STRB is a
handshake output line. In the input handshake
mode, the pin serves as a READY line, inhibiting
the external device from strobing data into Port C.
In the output handshake mode, STRB indicates that
new data has been written to Port B by the
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