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參數(shù)資料
| 型號(hào)： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 98K |
| 代理商： | TK68HC24 |
Tekmos
TK68HC24 PRU
16
www.Tekmos.com
8/21/99
Peripheral Port Timing
(Vdd = 5.0 V + 10%, all timing is shown with respect to 20% Vdd and 70% Vdd unless otherwise noted.)
Characteristics
Symbol
t
PDSU
t
PDH
t
PWD
Min
200
10
-
Max
-
-
100
Unit
ns
ns
ns
Fig. No.
4
4
3
Peripheral Data Setup Time (Post C)
Peripheral Data Hold Time (Post C)
Delay Time, E Negative Transition to
Peripheral Data Valid (Ports B and C,
see Note 1)
Input Data Setup Time (Port C)
Input Data Hold Time (Port C)
Delay Time, E Positive Transition to
STRB Asserted (see Note 1)
Delay Time, E Positive Transition to
STRB Negated Handshake Mode
(see Note 1)
Setup Time, STRA Asserted to E
Negative Transition (see Note 2)
Delay Time, STRA Asserted to Port C
Data Out Valid (see Note 3)
Hold Time, STRA Negated to Port C
Data
Three-State Hold Time
STRA Cycle Time
t
IS
t
IH
t
DEB
50
10
-
-
-
ns
ns
ns
6, 7
6, 7
5, 8, 9
80
t
DEBN
-
80
ns
7, 9
t
AES
0
-
ns
7, 8, 9
t
PCD
-
100
ns
9
t
PCH
10
-
ns
9
t
PCZ
t
Scyc
-
2
150
-
ns
E
cyc
9
6,7
Notes:
1. The method of calculating the timing for this characteristic differs from the 68HC11.
2. If this setup time is met, STRB will be acknowledged in the next cycle. If it is not met, the response will be
delayed one more cycle.
3. Port C timing is only valid for active drive (CWOM bit is not set in PIOC).
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