參數(shù)資料
型號(hào)： TK68HC24
廠商： Electronic Theatre Controls, Inc.
英文描述： Port Replacement Unit (PRU)
中文描述： 港口更換單元（普天壽）
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 98K
代理商： TK68HC24
Tekmos
TK68HC24 PRU
3
www.Tekmos.com
8/21/99
processor. The PLS bit of the PIOC register
controls whether this pin pulses or remains at a
level.
PB7 – PB0
Port B, Bits 7 to 0 - Outputs
An 8 bit, general purpose output port. STRB pulses
with each write to Port B in the simple strobed
mode of operation.
PC7 – PC0
Port C, Bits 7 to 0 - Bidirectional
This is a general purpose, 8-bit bidirectional port.
Each bit may be individually programmed by the
DDRC register to be either an input or an output.
Input data is read from the PORTCL register, while
output data is written to the Port C register. The
STRA pin serves as a handshake signal for this
port.
IRQN
Interrupt Request – Open drain, active low output
This pin provides the interrupt signal back to the
processor. It is a logical NAND of the STAF and
STAI bits in the PIOC register.
AS
Address Strobe - Input
This pin serves to de-multiplex the address form the
data on the AD bus. The falling edge of AS causes
the address to be latched internally within the
TK68HC24.
MODE
Mode Select - Input
The mode select pin is sampled at the rising edge
of reset. A zero puts the chip into a special
emulation mode, while a one leaves it in the normal
operating mode.
CSN / Chip Select
Input, active low
This is the device chip select. The TK68HC24 is
selected when 1) CSN is low, 2) the contents of the
INIT register match address lines A12 – A15, and 3)
when the lower order address lines (AD0 – AD7)
select an internal register. The CSN signal is
latched on the rising edge of the E clock.
RWN
Read / Write - Input
Determines whether data is being read from, or is
being written to the device.
E
Enable - Input
The E (Enable) pin is the clock for the TK68HC24.
The E clock runs at the external bus rate of the
6811 microprocessor.
RESETN
Active Low Input
The RESETN pin provides a synchronous reset to
the part. It must remain low for 2 E clock cycles in
order to be recognized.
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