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參數(shù)資料
| 型號： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 98K |
| 代理商： | TK68HC24 |
Tekmos
TK68HC24 PRU
7
www.Tekmos.com
8/21/99
strobe B output line is logic zero. This bit is
set to one by RESET so that the STRB
output will initially be in the low state out of
reset. For a more detailed description of
the handshake protocols, see the I/O
PORTS section.
PORT C DATA REGISTER (PORTC)
Reset value = 00000000
Port C (PORTC) is a general purpose input/output
Port Complemented by full handshake capability.
For bits that are configured as inputs, reads of this
address return the level sensed at the pin. For bits
configured as outputs, reads return the level sensed
at the input to the pin driver. When a Port C pin is
being used for the three-state variation of parallel
output handshake, reads return the level sensed at
the input to the pin driver even if the DDR bits
suggest that the pin is configured as an input.
Writes to Port C cause the value to be latched in
the 8-bit Port C data register. (Note that this is not
the same register as the PORTCL latch register
described later.) When the corresponding DDRC bit
is set, the value in the Port C data register is driven
out of the Port C pin. This data latch allows the
programmer to initialize the data prior to turning on
the output drivers by setting bits in the DDRC. The
PORTC register is cleared by RESET.
The Port C bits are labeled as PC7 – PC0.
PORT B DATA REGISTER (PORTB)
Reset value = 00000000
Port B (PORTB) is a general purpose output-only
port. Reads of this address return the level sensed
at the input to the pin driver. Writes to Port B cause
the value to be latched in the 8-bit Port B data
register. The PORTB register is set to zero by
RESET.
The Port B bits are labeled as PB7 – PB0.
PORT C LATCHED DATA REGISTER (PORTCL)
Reset value = XXXXXXXX (not reset)
The Port C latch register (PORTCL) allows
alternate access to Port C information. This
register is used in conjunction with the strobed
parallel I/O modes. Input data is latched into the
PORTCL register on each selected edge on the
STRA pin. The latched data is the level at the pins
regardless of the operating mode selected. Reads
of PORTCL return the contents of the Port C input
latch. Reads also act as part of an automatic flag
clearing sequence in the input handshake modes of
Port C.
Writes to the PORTCL register are equivalent to
writes to the PORTC register except the PORTCL
writes are used as part of an automatic flag clearing
sequence in the output handshake modes of Port
C. For more information on the Port C strobed and
handshake modes, see
I/O PORTS
. The contents
of PORTCL are not affected by RESET.
The Port CL bits are labeled as PCL7 – PCL0.
DATA DIRECTION REGISTER C (DDRC)
Reset value = 00000000
The data direction register C (DDRC) is a read/write
register used in conjunction with Port C to specify
the direction of data flow at each of the Port C pins.
A Port C pin is an input if the corresponding bit in
DDRC is zero. The pin is an output if the
corresponding bit in DDRC is set to one. During
reset, all bits in the DDRC are cleared to zero. The
effects of DDRC are overridden in the three-state
variation of the output handshake mode. For
additional information, see
I/O PORT OPERATION,
Output Handshake Protocol, Three-State
Variation
.
The port bits are labeled as DDRC7 – DDRC0.
HIGHEST PRIORITY INTERRUPT REGISTER
(HPRIO)
Reset value = 0*0*0000
Note that the reset condition of SMOD and IRV
depends on initialization mode.
SMOD
– Bit 6, Read / Write once
The SMOD (Special Test Mode) bit is a
read only bit which reflects the operating
mode of the peripheral as selected by the
MODE input. The inverted state of MODE
is latched in SMOD by the rising edge of
RESET. When SMOD equals zero (MODE
equals one), the peripheral is operating in
normal mode. When SMOD equals one
(MODE equals zero), the special test mode
is selected.
The special test mode may be exited under
software control by writing SMOD from a
one to a zero. However, the special test
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