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參數(shù)資料
| 型號(hào)： | TK68HC24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Port Replacement Unit (PRU) |
| 中文描述： | 港口更換單元（普天壽） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 98K |
| 代理商： | TK68HC24 |
Tekmos
TK68HC24 PRU
13
www.Tekmos.com
8/21/99
test mode. Entering the normal mode forces the
IRV bit to zero, enabling the data bus output buffers
on reads of these two addresses. Table 1
summarizes the chip select options.
Table 1. TK68HC24 Chip Select
Action Summary
CSN
IRV
Action Taken
0
0
Chip selected, HPRIO and
INIT reads enabled.
0
1
Chip selected. HPRIO and
INIT reads disabled
1
X
Chip not selected
NORMAL MODE
Normal mode is selected when the MODE input is
at a logic high level at the rising edge of RESET.
The HPRIO register is initialized to $00 (SMOD and
IRV equal zero). The INIT register write-protect
mechanism is enabled, allowing only a single write
to INIT. Reads of both the INIT and HPRIO register
enable the output buffers, thus providing visibility
into the contents of these registers. The HPRIO
register is write-protected while in the normal mode.
A reset sequence must be initiated to change the
contents of this register.
NOTE
A write to the INIT register must be
included in the initialization software
whether or not the registers are to be
relocated. This write will ensure that an
accidental write to register at a later time
will not cause the registers to be remapped.
THIS IS ONE OF THE FUNCTIONAL
DIFFERENCES BETWEEN THE 68HC11
PORTS AND THE TK68HC24
IMPLEMENTATION.
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