
Tekmos
TK68HC24 PRU
14
www.Tekmos.com
8/21/99
Differences Between the Motorola and Tekmos Version of the TK68HC24
1. The TK68HC24 is a new design, and is
manufactured in a 0.8u CMOS process. The
design has been modified to compensate for
the faster process in order to retain
compatibility with the older parts.
2. All inputs now have Schmitt triggers. Inputs
fabricated on the new process will be faster.
That makes them more sensitive to noise
spikes, and they require faster rise times to
avoid input oscillation. The insertion of Schmitt
triggers on all inputs and bi-directional signals
removes this sensitivity. The new parts still
meet all of the original input level specifications.
3. Reset has been modified. In the original circuit,
it was possible to trigger a partial chip reset by
the presence of a well placed glitch on the reset
line. The faster Tekmos implementation might
respond to noise on the reset line that would
not affect the original parts. The modification
requires the presence of reset for at least 1/2 E
clock before it is recognized. This is consistent
with the specification, which requires users to
keep the E clock low for two entire clock cycles.
4. The IOTEST pin has been removed from the
documentation. This pin was not present on
the old 68HC24s.
68HC11 And TK68HC24 Operational Differences
INIT REGISTER WRITE-PROTECT MECHANISM
The 68HC11 INIT register write-protect mechanism
automatically disables writes to the INIT register 64
E clock cycles after the rising edge of RESET. The
TK68HC24 write-protect circuitry IS NOT TIME
DEPENDENT. Only a write to the INIT register will
disable further writes. Both the 68HC11 and
TK68HC24 INIT registers can be written repeatedly
in the special test mode of operation (see SPECIAL
TEST MODE) or once in the normal mode.
This difference dictates that the user should not rely
on the timeout feature of the 68HC11 to write-
protect the INIT register if he plans to utilize the
same software with the TK68HC24. Instead, a
write to the INIT register should be done during
initialization, even if the remapping feature is not
going to be used.
STRA PULSE WIDTH
Due to differences in implementation technology,
the TK68HC24 incorporates an additional level of
synchronization (over the 68HC11) on the STRA
input. Under normal operating conditions, the end
user will be unaware of this anomaly. Only systems
which continually strobe new data into PORTCL are
affected.
In order to allow the STRA signal to propagate
through the internal feedback mechanism, a
minimum delay of two E-clock cycles between
active edges has been specified. This delay should
not concern most users, since the time required to
acknowledge the receipt of data and to read the
data is much greater that two cycles.
STRB SYNCHRONIZATION
The 68HC11 synchronizes changes of Port B, Port
C, and STRB data to an internal quadrature clock.
This method of implementation makes internal
buffer delays transparent to the end user. This
internal clock is generated from the 4X clock, and
as a result, cannot be duplicated by the TK68HC24.
Port B and Port C data are synchronized to the E
clock and become valid t
PWD
after the falling edge of
E instead of a setup time before the falling edge of
E.
The most noticeable change involves STRB. The
STRB signal is synchronized to the rising edge of E
instead of the quadrature clock as in the 68HC11.
At slow clock rates (much less than 1MHz), the
delay between valid data on the port pins and the
assertion of STRB could be considerable.