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參數(shù)資料
| 型號(hào)： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁(yè)數(shù)： | 38/46頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
38/46
10.8.4 - Composite output
HLckVBk
The composite output
HLckVBk
provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic di-
agram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in
Figure 15
, the combinations, their respective
levels and the
HLckVBk
configuration in
Figure 16
.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator dis-
charge. The combination corresponds to the draw-
ing in
Figure 16
. The blanking pulse is started with
Figure 16.
Levels on HLckVBk composite output
the leading edge of any of the two signals, which-
ever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of
BlankMode
I
2
C bus bit, when
at 1 (default), the blanking level (one of two ac-
cording to PLL1 status) is made available on the
HLckVBk
permanently. The permanent blanking,
irrespective of the
BlankMode
I
2
C bus bit, is also
provided if the supply voltage is low (under
V
or
V
CCDis
thresholds), if the X-ray protection is ac-
tive or if the V-drive signal is disabled by
VOutEn
I
2
C bus bit.
HLckVBk
3
V
CC
HPLL1 locked
V-early blanking
Yes
Yes
No
Yes
No
No
Yes
No
I
SinkLckBlk
V
OLckBlk
L1
(H)
+L2
(L)
L1
(L)
+L2
(H)
L1
(H)
+L2
(H)
L1
(L)
+L2
(L)
L1 - No blank/blank level
L2 - H-lock/unlock level
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