參數(shù)資料
型號： STV9118
廠商： 意法半導(dǎo)體
英文描述： LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
中文描述： 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器
文件頁數(shù)： 12/46頁
文件大小： 577K
代理商： STV9118
STV9118
12/46
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in R
RO
and C
CO
positions so as to always meet this condition. The formula to calculate
the free-running frequency is
f
HO(0)
=0.12125/(R
RO
C
CO
)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500
and a resistance to ground of about 20k
.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on
HPLL2C
pin corresponds to immediate phase of leading edge of H-drive signal on
HOut
pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See
Figure 10
.
Note 7: The
t
ph
(min)/T
H
parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of
V
TopHPLL2C
high clamping level by waveform on pin
HPLL2C
. Also refer to
Note 5
and
Figure 10
.
Note 8: The
t
ph
(max)/T
H
parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of
V
BotHPLL2C
low clamping level by waveform on pin
HPLL2C
. Also refer to
Note 5
and
Figure 10
.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
7.5 - VERTICAL SECTION
V
CC
= 12V, T
amb
= 25°C
t
PCAC
/T
H
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
PCAC
(Sad11h) full span
(
9
)
VPOS
at medium
VSIZE
at minimum
VSIZE
at medium
VSIZE
at maximum
PARAL
(Sad12h) full span
(
9
)
VPOS
at medium
VSIZE
at minimum
VSIZE
at medium
VSIZE
at maximum
VPOS
at max. or min.
VSIZE
at minimum
±1.0
±1.8
±2.8
%
%
%
t
ParalC
/T
H
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
±1.75
±2.2
±2.8
±1.75
%
%
%
%
Symbol
Parameter
Test Conditions
Value
Units
Min.
Typ.
Max.
Symbol
Parameter
Test Conditions
Value
Units
Min.
Typ.
Max.
AGC-controlled vertical oscillator sawtooth;
V
RefO
= 8V
Ext. load resistance on
VAGCCap
pin
(
10
)
Sawtooth bottom voltage on
VCap
pin
(
11
)
R
L(VAGCCap)
V
amp
/V
amp
(R=
∞
)
≤
1%
65
M
V
VOB
No load on
VOscF
pin
(
11
)
2
V
V
VOT
Sawtooth top voltage on
VCap
pin
AGC loop stabilized
V sync present
No V sync
5
4.9
V
V
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