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參數(shù)資料
| 型號： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
26/46
Figure 2.
Horizontal sync signal
10.2.2 - Sync. presence detection flags
The sync. signal presence detection flags in the
status register (
VDet
,
HVDet
,
VExtrDet
) do not
show in real time the presence or absence of the
corresponding sync. signal. They are latched to 1
as soon as a single sync. pulse is detected. In or-
Figure 3.
Extraction of V-sync signal from H/V-sync signal
der to reset them to 0 (all at once), a 1 must be
written into
SDetReset
I
2
C bus bit, the reset action
taking effect with ACK bit of the I
2
C bus transfer to
the register containing the
SDetReset
bit. The de-
tection circuits are then ready to capture another
event (pulse). See
Note 47
.
10.2.3 - MCU controlled sync. selection mode
I
2
C bus bit
VSyncAuto
is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the
SDetReset
bit to 1 and an appro-
priate delay, to obtain a true information of the sig-
nals applied, reads and evaluates this information
and controls the vertical signal selector according-
ly. The MCU has no access to polarity inverters,
they are controlled automatically.
See also chapter
I
2
C BUS CONTROL REGISTER
MAP
on
page 21
.
10.2.4 - Automatic sync. selection mode
I
2
C bus bit
VSyncAuto
is set to 1. In this mode, the
device itself controls the I
2
C bus bits switching the
polarity inverters (
HVPol
,
VPol
) and the vertical
sync. signal selector (
VSyncSel
), using the infor-
mation provided by detection circuitry. If both ex-
tracted and pure vertical sync. signals are present,
the one already selected is maintained. No inter-
vention of the MCU is necessary.
10.3 - HORIZONTAL SECTION
10.3.1 - General
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-
ing and output driving circuitry providing H-drive
signal on
HOut
pin. Input signal to the horizontal
section is output of the polarity inverter on
H/
HVSyn
input. The device ensures automatically
that this polarity be always positive.
10.3.2 - PLL1
The PLL1 block diagram is in
Figure 5
. It consists
of a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhi-
bition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal, with a possibility to adjust a perma-
nent phase offset. On the screen, this offset re-
Positive
Negative
T
H
t
PulseHSyn
H/V-sync
Integration
Extracted
V-sync
t
extrV
T
H
t
PulseHsyn
Internal
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