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參數(shù)資料
| 型號(hào)： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁(yè)數(shù)： | 11/46頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
11/46
7.4 - HORIZONTAL SECTION
Vcc = 12V, T
amb
= 25°C
Symbol
Parameter
Test Conditions
Value
Units
Min.
Typ.
Max.
PLL1
I
RO
C
CO
f
HO
f
HO(0)
f
HOCapt
Current load on
RO
pin
Capacitance on
CO
pin
Frequency of hor. oscillator
Free-running frequency of hor. oscill.
(
1
)
Hor. PLL1 capture frequency
(
4
)
1.5
mA
pF
kHz
kHz
kHz
390
100
29.9
122
R
RO
=5.23k
, C
CO
=820pF
f
HO(0)
= 28.5kHz
27
29
28.5
Temperature drift of free-running freq.
(
3
)
-150
ppm/°C
f
HO
/
V
HO
V
HO
Average horizontal oscillator sensitivity
H. oscill. control voltage on pin
HPLL1F
Threshold on H. oscill. control voltage on
HPLL1F
pin for tracking of EW with freq.
f
HO(0)
= 28.5kHz
V
RefO
=8V
19.6
kHz/V
V
1.4
6.0
V
HOThrfr
V
RefO
=8V
5.0
V
V
HPosF
Control voltage on
HPosF
pin
HPOS
(Sad01):
1111111xb
1000000xb
0000000xb
2.8
3.4
4.0
1.6
6.4
V
V
V
V
V
V
HOThrLo
V
HOThrHi
PLL2
R
In(HFly)
I
InHFly
V
ThrHFly
Bottom of hor. oscillator sawtooth
(
6
)
Top of hor. oscillator sawtooth
(
6
)
Input impedance on
HFly
input
Current into
HFly
input
Voltage threshold on
HFly
input
V
(HFly)
>
V
ThrHFly
(
2
)
At top of H flyback pulse
300
500
700
5
mA
V
0.6
0.7
V
S(0)
H flyback lock middle point
(
6
)
No PLL2 phase modula-
tion
4.0
V
V
BotHPLL2C
V
TopHPLL2C
Low clamping voltage on
HPLL2C
pin
(
5
)
High clamping voltage on
HPLL2C
pin
(
5
)
Min. advance of H-drive OFF before
middle of H flyback
(
7
)
Max. advance of H-drive OFF before
middle of H flyback
(
8
)
H-drive output on pin
HOut
I
HOut
Current into
HOut
output
1.6
4.0
V
V
t
ph
(min)/T
H
Null asym. correction
0
%
t
ph
(max)/T
H
Null asym. correction
44
%
Output driven LOW
HDUTY
(Sad00):
x1111111b
x0000000b
Soft-start/Soft-stop value
30
mA
t
Hoff
/T
H
Duty cycle of H-drive signal
27
65
85
%
%
%
Picture geometry corrections through PLL1 & PLL2
t
Hph
/T
H
H-flyback (center) static phase vs. sync
signal (via PLL1), see
Figure 7
HPOS
(Sad01):
1111111xb
0000000xb
+11
-11
%
%
f
f
HO 0
T
----------------------------
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