參數(shù)資料
型號： STV9118
廠商： 意法半導(dǎo)體
英文描述： LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
中文描述： 低費用的I2C可控?fù)隙榷嗤斤@示器處理器
文件頁數(shù)： 23/46頁
文件大小： 577K
代理商： STV9118
STV9118
23/46
Sad16/D1 -
PLL1InhEn
En
able of
Inh
ibition of horizontal
PLL1
during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad16/D2 -
PLL1Pump
Horizontal
PLL1
charge
Pump
current
0: Slow PLL1, low current
1: Fast PLL1, high current
Sad16/D3 -
HMoiMode
H
orizontal
Moi
ré
Mode
. In position “Internal”, the
H-moiré signal affects timing of H-drive signal on
HOut
pin. In position “External”, the H-moiré sig-
nal is output on
HMoiré
pin and has no effect on
H-drive. In both cases, the amplitude of H-moiré
signal is adjusted through I
2
C Bus register
HMOIRE
.
0: Internal
1: External
Sad16/D4 -
SDetReset
Reset
to 0 of
S
ynchronization
Det
ection flags
VDet
,
HVDet
and
VExtrDet
of status register ef-
fected with ACK bit of I
2
C Bus data transfer into
register containing the
SDetReset
bit. Also see
description of the flags.
0: No effect
1: Reset with automatic return of the bit to 0
Sad16/D5 -
VSyncSel
V
ertical
Sync
hronization input
Sel
ection be-
tween the one extracted from composite HV sig-
nal on pin
H/HVSyn
and the one on pin
VSyn
.
No effect if
VSyncAuto
bit is at 1.
0: V. sync extracted from composite signal on
H/HVSyn
pin selected
1: V. sync applied on
VSyn
pin selected
Sad16/D6 -
VSyncAuto
V
ertical
Sync
hronization input selection
Auto-
matic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin
H/HVSyn
and the
one on pin
VSyn
, based on detection mecha-
nism. If both are present, the one coming first is
kept.
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit
VSyncSel
has no effect
Sad16/D7 -
XRayReset
Reset
to 0 of
XRay
flag of status register effect-
ed with ACK bit of I
2
C Bus data transfer into reg-
ister containing the
XRayReset
bit. Also see de-
scription of the flag.
0: No effect
1: Reset with automatic return of the bit to 0
Sad17/D0 -
BlankMode
Blank
ing operation
Mode
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start of vertical sawtooth ramp on the
VOut
pin)
1: Permanent blanking - high blanking level in
composite signal on pin
HLckVBk
is per-
manent
Sad17/D1 -
VOutEn
V
ertical
Out
put
En
able
0: Disabled,
V
offVOut
on
VOut
pin (see 7.5 -
Vertical section)
1: Enabled, vertical ramp with vertical position
offset on
VOut
pin
Sad17/D2 -
HBOutEn
H
orizontal and
B
+
Out
put
En
able
0: Disabled, levels corresponding to “power
transistor off” on
HOut
and
BOut
pins (high
for
HOut
, low for
BOut
).
1: Enabled, horizontal deflection drive signal
on
HOut
pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on
BOut
pin.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in ex-
ternal sawtooth configuration.
Sad17/D3 -
BOHEdge
Selection of
Edge
of
H
orizontal drive signal to
phase
B
+ drive
O
utput signal on
BOut
pin. Only
applies if the bit
BOutPh
is set to 1, otherwise
BOHEdge
has no effect.
0: Falling edge
1: Rising edge
Sad17/D4,D5,D6,D7 -
THM
,
TVM
,
TH
,
TV
Test bits. They must be kept at 0 level by appli-
cation S/W.
Read-out flags
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