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參數(shù)資料
| 型號： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費用的I2C可控撓度多同步顯示器處理器 |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
25/46
10 - OPERATING DESCRIPTION
10.1 - SUPPLY AND CONTROL
10.1.1 - Power supply and voltage references
The device is designed for a typical value of power supply
voltage of 12 V.
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
V
CC
is monitored. See
Figure 1
and electrical
specifications. At switch-on, the device enters a
“normal operation” as the supply voltage exceeds
V
CCEn
and stays there until it decreases bellow
V
CCDis
. The two thresholds provide, by their differ-
ence, a hysteresis to bridge potential noise. Out-
side the “normal operation”, the signals on
HOut
,
BOut
and
VOut
outputs are inhibited and the I
2
C
bus interface is inactive (high impedance on
SDA
,
SCL
pins, no ACK), all I
2
C bus control registers
being reset to their default values (see chapter
I
2
C
BUS CONTROL REGISTER MAP
on
page 21
).
Figure 1.
Supply voltage monitoring
Internal thresholds in all parts of the circuit are de-
rived from a common internal reference supply
V
RefO
that is lead out to
RefOut
pin for external fil-
tering against ground as well as for external use
with load currents limited to
I
RefO
. The filtering is
necessary to minimize interference in output sig-
nals, causing adverse effects like e.g. jitter.
10.1.2 - I
2
C Bus Control
The I
2
C
bus is a 2 line bi-directional serial commu-
nication bus introduced by Philips. For its general
description, refer to corresponding Philips I
2
C bus
specification.
This device is an I
2
C bus slave, compatible with
fast (400kHz) I
2
C bus protocol, with write mode
slave address of 8C (read mode slave address
8D). Integrators are employed at the
SCL
(Serial
Clock) input and at the input buffer of the
SDA
(Se-
rial Data) input/output to filter off the spikes of up to
50ns.
The device supports multiple data byte messages
(with automatic incrementation of the I
2
C bus sub-
address) as well as repeated Start Condition for
I
2
C bus subaddress change inside the I
2
C bus
messages. All I
2
C bus registers with specified I
2
C
bus subaddress are of WRITE ONLY type, where-
as the status register providing a feedback infor-
mation to the master I
2
C bus device has no attrib-
uted I
2
C bus subaddress and is of READ ONLY
type. The master I
2
C bus device reads this register
sending directly, after the Start Condition, the
READ device I
2
C bus slave address (8D) followed
by the register read-out, NAK (No Acknowledge)
signal and the Stop Condition.
For the I
2
C bus control register map, refer to chap-
ter
I
2
C BUS CONTROL REGISTER MAP
on
page 21
.
10.2 - SYNC. PROCESSOR
10.2.1 - Synchronization signals
The device has two inputs for TTL-level synchroni-
zation signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On
H/
HVSyn
input, pure horizontal or composite hori-
zontal/vertical signal is accepted. On
VSyn
input,
only pure vertical sync. signal is accepted. Both
positive and negative polarities may be applied on
either input, see
Figure 2
. Polarity detector and
programmable inverter are provided on each of
the two inputs. The signal applied on
H/HVSyn
pin,
after polarity treatment, is directly lead to horizon-
tal part and to an extractor of vertical sync. pulses,
working on principle of integration, see
Figure 3
.
The vertical sync. signal applied to the vertical de-
flection processor is selected between the signal
extracted from the composite signal on
H/HVSyn
input and the one applied on
VSyn
input. The se-
lector is controlled by
VSyncSel
I
2
C bus bit.
Besides the polarity detection, the device is capa-
ble of detecting the presence of sync. signals on
each of the inputs and at the output of vertical
sync. extractor. The information from all detectors
is provided in the I
2
C bus status register (5 flags:
VDet
,
HVDet
,
VExtrDet
,
VPol
,
HVPol
). The device
is equipped with an automatic mode (switched on
or off by
VSyncAuto
I
2
C bus bit) that also uses the
detection information.
Normal operation
hysteresis
V
CCEn
V
CCDis
t
Disabled
Disabled
V
(Vcc)
V
CC
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