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參數(shù)資料
| 型號(hào)： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁(yè)數(shù)： | 30/46頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
30/46
The behaviour of horizontal moiré is to be opti-
mised for different deflection design configurations
using
HMoiré
I
2
C bus bit. This bit is to be kept at 0
Figure 10.
Control of HOut and BOut at start/stop at nominal V
cc
for common architecture (B+ and EHT common
regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).
10.4 - VERTICAL SECTION
10.4.1 - General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de-
flection frequency, on which vertical geometry cor-
rections of C- and S-type are superimposed (see
chapter
TYPICAL OUTPUT WAVEFORMS
).
Block diagram is in
Figure 11
. The sawtooth is ob-
tained by charging an external capacitor on pin
VCap
with controlled current and by discharging it
via transistor Q1. This is controlled by the CON-
TROLLER. The charging starts when the voltage
across the capacitor drops below
V
VOB
threshold.
The discharging starts either when it exceeds
V
VOT
threshold or a short time after arrival of synchroni-
zation pulse. This time is necessary for the AGC
loop to sample the voltage at the top of the saw-
tooth. The
V
reference is routed out onto
VO-
scF
pin in order to allow for further filtration.
The charging current influences amplitude and
shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin
VCap
is
sampled and stored on a storage capacitor con-
nected on pin
VAGCCap
. During the following ver-
tical period, this voltage is compared to internal
reference REF (
V
VOT
), the result thereof control-
ling the gain of the transconductance amplifier pro-
viding the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap
. The
VLock
I
2
C bus flag is set to 1
when the loop is stabilized, i.e. when the voltage
on pin
VAGCCap
matches
V
VOT
value. On the
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop sta-
bility. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor re-
sults in difference in amplitude between low and
high frequencies. The higher its parallel resistance
R
L(VAGCCap)
, the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency
f
VO(0)
only depends on the
value of the capacitor on pin
VCap
. It can be
roughly calculated using the following formula
f
VO(0)
=
t
V
(HPosF)
Soft start
Soft stop
Normal operation
Start
HOut
Start
BOut
Stop
HOut
Stop
BOut
HOut
H-duty cycle
BOut
B-duty cycle
100%
0%
V
HOn
V
BOn
V
HBNorm
V
HPosMax
V
HPosMin
HPOS(I
2
C)
range
minimum value
maximum value
C
(VCap)
.100Hz
150nF
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