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參數(shù)資料
| 型號(hào)： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁數(shù)： | 35/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | STV9118 |
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STV9118
35/46
During the operation, a sawtooth is to be found on
pin
BISense
, generated externally by the applica-
tion. According to
BOutPh
I
2
C bus bit, the R-S flip-
flop is set either at H-drive signal edge (rising or
falling, depending on
BOHEdge
I
2
C bus bit), or a
certain delay (
t
BTrigDel
/ T
H
) after middle of H-fly-
back. The output is set On at the end of a short
pulse generated by the monostable trigger.
Timing of reset of the R-S flip-flop affects duty cy-
cle of the output square signal and so the energy
transferred from DC/DC converter input to its out-
put. A reset edge is provided by comparator C2
if
the voltage on pin
BISense
exceeds the internal
threshold
V
ThrBIsCurr
. This represents current limi-
tation if a voltage proportional to the current
through the power component or deflection stage
is available on pin
BISense
. This threshold is af-
fected by the voltage on pin
HPosF
, which rises at
soft start and descends at soft stop. This ensures
self-contained soft control of duty cycle of the out-
put signal on pin
BOut
. Refer to
Figure 10
. Another
condition for the reset of the R-S flip-flop, OR-ed
Figure 14.
DC/DC converter controller block diagram
with the one described before, is that the voltage
on pin
BISense
exceeds the voltage V
C1
, which
depends on the voltage applied on input
BISense
of the error amplifier O1. The two voltages are
compared, and the reset signal generated by the
comparator C1. The error amplifier amplifies (with
a factor defined by external components) the dif-
ference between the input voltage proportional to
DC/DC convertor output voltage and internal refer-
ence
V
BReg
. The internal reference and so the out-
put voltage is I
2
C bus adjustable by means of
BREF
I
2
C bus control.
DC/DC controller Off-to-On edge timing
BOutPh
(Sad07/
D7)
D3)
0
don’t care Middle of H-flyback plus t
BTrigDel
1
0
Falling edge of H-drive signal
1
1
Rising edge of H-drive signal
BOHEdge
(Sad17/
Timing of Off-to-On transition
on BOut output
C1
BRegIn
BComp
V
ThrBIsCurr
BIsense
BOut
Soft start
H-drive edge
H-flyback
(+delay)
+
-
+
-
+
-
S
Q
R
~500ns
Monostable
HBOutEn
XRayAlarm
(I
2
C)
V
CC
Feedback
C2
BOutPh
(I
2
C)
HPosF
BOHEdge
(I
2
C)
2R
R
V
BReg
I1
V
C1
O1
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