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參數(shù)資料
| 型號(hào)： | STV9118 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費(fèi)用的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大小： | 577K |
| 代理商： | STV9118 |
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STV9118
24/46
SadXX/D0 -
VDet
(
47
)
Flag indicating
Det
ection of
V
synchronization
pulses on
VSyn
pin.
0: Not detected
1: Detected
SadXX/D1 -
HVDet
(
47
)
Flag indicating
Det
ection of
H
or H
V
synchroni-
zation pulses applied on
H/HVSyn
pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
SadXX/D2 -
VExtrDet
(
47
)
Flag indicating
Det
ection of
Extr
acted
V
ertical
synchronization signal from composite H+V sig-
nal applied on
H/HVSyn
pin
0: Not detected
1: Detected
SadXX/D3 -
VPol
Flag indicating
Pol
arity of
V
synchronization
pulses applied on
VSyn
pin with respect to mean
level of the sync signal
0: Positive
1: Negative
Note 47: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the
SDetReset
I
2
C Bus bit). This is to be taken into account by application S/W in a way
that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through
SDetReset
bit and validation of information provided in the flag after read-
out of status register.
SadXX/D4 -
HVPol
Flag indicating
Pol
arity of
H
or H
V
synchroniza-
tion pulses applied on
H/HVSyn
pin with respect
to mean level of the sync signal
0: Positive
1: Negative
SadXX/D5 -
XRayAlarm
Alarm
indicating that an event of excessive volt-
age has passed on
XRay
pin. Can only be reset
to 0 through I
2
C Bus bit XRayReset or by power-
on reset.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit,
HOut
inhibited
SadXX/D6 -
VLock
Status of “
Lock
ing” or stabilization of
V
ertical os-
cillator amplitude to an internal reference by
AGC regulation loop.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 -
HLock
Status of
Loc
king of
H
orizontal PLL1
0: Locked
1: Not locked
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