參數(shù)資料
型號: STPCE1HDC
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 75/87頁
文件大小: 1356K
代理商: STPCE1HDC
DESIGN GUIDELINES
Release 1.3 - January 29, 2002
75/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.4.3. PCI INTERFACE
6.4.3.1. Introduction
In order to achieve a PCI interface which work at
clock
frequencies
up
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
to
33MHz,
careful
6.4.3.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
0
and T
1
.
Figure 6-21. Clock Scheme
HCLK PLL
1/2
1/3
1/4
clock
delay
Strap Options
PCICLKO
T
1
PCICLKI
HCLK
AD[31:0]
South
Bridge
North
Bridge
Deskewer
MUX
T
0
T
2
STPC
MD[30:27]
MD[17,4]
MD[7:6]
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