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參數(shù)資料

型號(hào)：	STPCE1HDC
英文描述：	Microprocessor
中文描述：	微處理器
文件頁(yè)數(shù)：	2/87頁(yè)
文件大?。?/td>	1356K
代理商：	STPCE1HDC

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2/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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X86 Processor core

Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

Can access up to 4GB of external memory.

8KByte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

Clock core speeds up to of 100 MHz in x1

clock mode and 133MHz in x2 mode.

Fully static design for dynamic clock control.

Low power and system management modes.

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SDRAM Controller

64-bit data bus.

Up to 100MHz SDRAM clock speed.

Supports up to 128 MB system memory.

Supports 16-, 64- and 128-Mbit memories.

Supports up to 4 memory banks.

Supports buffered, non buffered, registered

DIMMs

4-line write buffers for CPU to DRAM and PCI

to DRAM cycles.

4-line read prefetch buffers for PCI masters.

Programmable latency

Programmable timing for DRAM parameters.

Supports -8, -10, -12, -13, -15 memory parts

Supports memory hole between 1MB and

8MB for PCI/ISA busses.

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PCI Controller

Compliant with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic

allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

Support for burst read/write from PCI master.

0.25X, 0.33X and 0.5X Host clock PCI clock.

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ISA master/slave

Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back

I/O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

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Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host

bus. NSP compliant.

16-bit I/O decoding.

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Local Bus interface

Multiplexed with ISA/DMA/Timer functions.

High speed, low latency bus.

Supports 32-bit Flash burst.

16-bit data bus with word steering capability.

Separate memory and I/O address spaces.

Programmable timing (Host clock granularity)

Supports 2 cachable banks of 16MB flash

devices with boot block shadowed to

0x000F0000.

2 Programmable Flash/EPROM Chip Select.

4 Programmable I/O Chip Select.

2-level hardware key protection for Flash boot

block protection.

24 bit address bus.

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EIDE Controller

Compatible with EIDE (ATA-2).

Backward compatibility with IDE (ATA-1).

Supports up to 4 IDE devices

Supports PIO and Bus Master IDE

Concurrent channel operation (PIO & DMA

modes) - 4 x 32-Bit Buffer FIFO per channel

Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

Bus Master with scatter/gather capability.

Multi-word DMA support for fast IDE drives.

Individual drive timing for all four IDE devices.

Supports both legacy & native IDE modes.

Supports hard drives larger than 528MB.

Support for CD-ROM and tape peripherals.

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Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA

controller.

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Supports external RTC.

Power Management

Four power saving modes: On, Doze,

Standby, Suspend.

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相關(guān)PDF資料	PDF描述
STPCELITE	X86 Core General Purpose PC Compatible System - on - Chip
STPCE1EDBI	X86 Core General Purpose PC Compatible System - on - Chip
STPCE1EEBC	X86 Core General Purpose PC Compatible System - on - Chip
STPCE1EEBI	X86 Core General Purpose PC Compatible System - on - Chip
STPCE1HEBC	X86 Core General Purpose PC Compatible System - on - Chip

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
STPCE1HEBC	功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCE1HEBI	功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCELITE	制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
STPCH0.5MBBL	制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
STPCH0.5MBBU	制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U

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