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參數(shù)資料
| 型號(hào)： | STPCE1EDBI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | X86 Core General Purpose PC Compatible System - on - Chip |
| 中文描述： | x86內(nèi)核兼容的通用計(jì)算機(jī)系統(tǒng)-關(guān)于-芯片 |
| 文件頁(yè)數(shù)： | 64/87頁(yè) |
| 文件大?。?/td> | 1356K |
| 代理商： | STPCE1EDBI |
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DESIGN GUIDELINES
64/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
multiplexing and address mapping described in
the following
Table 6-4
and
Table 6-5
.
Table 6-4. DIMM Pinout
SDRAM Density
Internal Banks
DIMM Pin Number
...
123
126
39
122
16 Mbit
2 Banks
64/128 Mbit
2 Banks
64/128 Mbit
4 Banks
STPC I/F
MA[10:0]
-
-
-
BA0 (MA11)
MA[10:0]
MA11
MA12
-
BA0 (MA13)
MA[10:0]
MA11
-
BA1 (MA12)
BA0 (MA13)
MA[10:0]
CS2# (MA11)
CS3# (MA12)
CS3# (BA1)
BA0
Table 6-5. Address Mapping
Address Mapping: 16 Mbit - 2 internal banks
STPC I/F
BA0
RAS Address
A11
CAS Address
A11
Address Mapping: 64/128 Mbit - 2 internal banks
STPC I/F
BA0
MA12 MA11 MA10 MA9
RAS Address
A11
A24
CAS Address
A11
0
Address Mapping: 64/128 Mbit - 4 internal banks
STPC I/F
BA0
BA1
RAS Address
A11
A12
CAS Address
A11
A12
MA10 MA9
A22
0
MA8
A2
A23
MA7
A19
A10
MA6
A18
A9
MA5
A17
A8
MA4
A16
A7
MA3
A15
A6
MA2
A14
A5
MA1
A13
A4
MA0
A12
A3
A21
A24
MA8
A20
A25
MA7
A19
A10
MA6
A18
A9
MA5
A17
A8
MA4
A16
A7
MA3
A15
A6
MA2
A14
A5
MA1
A13
A4
MA0
A12
A3
A23
0
A22
0
A21
A26
MA11 MA10 MA9
A24
A23
0
0
MA8
A21
A25
MA7
A20
A10
MA6
A19
A9
MA5
A18
A8
MA4
A17
A7
MA3
A16
A6
MA2
A15
A5
MA1
A14
A4
MA0
A13
A3
A22
A26
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