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參數(shù)資料
| 型號(hào)： | STPCE1EDBI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | X86 Core General Purpose PC Compatible System - on - Chip |
| 中文描述： | x86內(nèi)核兼容的通用計(jì)算機(jī)系統(tǒng)-關(guān)于-芯片 |
| 文件頁(yè)數(shù)： | 40/87頁(yè) |
| 文件大小： | 1356K |
| 代理商： | STPCE1EDBI |
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ELECTRICAL SPECIFICATIONS
40/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
4.5.3. SDRAM INTERFACE
Figure 4-5
and
Table 4-8
list the AC characteris-
tics of the SDRAM interface. The MCLKx clocks
are the input clock of the SDRAM devices
The PC133 memory is recommended to reach
100MHz operation.
Figure 4-5. SDRAM Timing Diagram
MCLKI
STPC.output
STPC.input
MCLKx
T
delay
T
setup
T
hold
T
output (min)
T
output (max)
T
cycle
T
high
T
low
Table 4-8. SDRAM Bus AC Timing
Name
Tcycle
Thigh
Tlow
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to Outputs Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MD[63:0] setup to MCKLI without RDCLK
MD[63:0] hold from MCKLI without RDCLK
Note: These timing are for a load of 50pF.
Min
10
4
4
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
Tdelay
-2
Toutput
5.2
4.7
5.1
0.8
0.8
8.7
10.9
10.9
1.8
1.6
Tsetup
Thold
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