參數資料
型號: STPCE1EDBI
廠商: 意法半導體
英文描述: X86 Core General Purpose PC Compatible System - on - Chip
中文描述: x86內核兼容的通用計算機系統(tǒng)-關于-芯片
文件頁數: 27/87頁
文件大?。?/td> 1356K
代理商: STPCE1EDBI
STRAP OPTION
Release 1.3 - January 29, 2002
27/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
3. STRAP OPTION
This chapter defines the STPC Elite Strap Options
and their location. Some strap options have been
left programmable for future versions of silicon..
Table 3-1. Strap Options
Signal
MD2
MD3
MD4
MD5
MD6
MD7
MD10
MD11
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
TC
Designation
Actual Settings
1
User defined
User defined
User defined
User defined
User defined
Pull down
Pull down
Pull down
Pull up
User defined
Pull Up
Pull Up
Pull Up
Pull Up
Pull up
Pull up
User defined
User defined
User defined
Pull down
Pull down
Pull down
Pull down
User defined
Pull down
Pull up
Pull down
User defined
Pull down
Pull up
Pull down
Pull up
Pull up
Pull up
Set to’0’
see
Section 3.1.4.
bit 6
see
Section 3.1.4.
bit 7
see
Section 3.1.1.
bit 4
Async
see
Section 3.1.1.
bit 6
-
-
-
-
see
Section 3.1.3.
bit 1
-
-
-
-
-
-
see
Section 3.1.4.
bit 3
see
Section 3.1.4.
bit 4
see
Section 3.1.4.
bit 5
Set to’1’
HCLK_PLL speed
PCI_CLKO divisor
MCLK/HCLK Sync (see
Section 3.1.1.
)
PCI_CLKO setup
Reserved
Reserved
Reserved
Reserved
PCI_CLKO divisor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Sync
-
-
-
-
-
-
-
-
-
-
HCLK PLL speed
Reserved
Reserved
Reserved
Reserved
CPU clock multiplication factor
Reserved
Reserved
Reserved
Bus select
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X1
-
-
-
ISA
-
-
-
-
X2
-
-
-
Local Bus
-
-
-
-
DACK_ENC[2:0]
Note
1
: Where a strap is represented by a ’Pull up’ or ’Pull down’, these have to be adhered to. If it is represented as a ’-
’ it can be left unconnected. Where ’User defined’, the strap is set by the user.
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