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參數(shù)資料
| 型號： | STPCC0390BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 7/59頁 |
| 文件大?。?/td> | 932K |
| 代理商： | STPCC0390BTC3 |
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PIN DESCRIPTION
Issue 1.1 - October 16, 2000
15/59
ter or an ISA master cycles by the STPC Consum-
er-S. ALE is driven low after reset.
MEMR#
Memory Read. This is the memory read
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write. This is the memory write
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
SMEMR#
System Memory Read.The STPC Con-
sumer-S generates SMEMR# signal of the ISA
bus only when the address is below one megabyte
or the cycle is a refresh cycle.
SMEMW# System Memory Write.The STPC Con-
sumer-S generates SMEMW# signal of the ISA
bus only when the address is below one mega-
byte.
IOR#
I/O Read. This is the IO read command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
IOW# I/O Write. This is the IO write command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
MCS16#
Memory Chip Select16. This is the de-
code of LA23-17 address pins of the ISA address
bus without any qualification of the command sig-
nal lines. MCS16# is always an input. The STPC
Consumer-S ignores this signal during IO and re-
fresh cycles.
IOCS16#
IO Chip Select16. This signal is the de-
code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig-
nals. The STPC Consumer-S does not drive
IOCS16# (similar to PC-AT design). An ISA mas-
ter access to an internal register of the STPC Con-
sumer-S is executed as an extended 8-bit IO cy-
cle.
BHE# System Bus High Enable.This signal, when
asserted, indicates that a data byte is being trans-
ferred on SD15-8 lines. It is used as an input when
an ISA master owns the bus and is an output at all
other times.
ZWS#
Zero Wait State. This signal, when assert-
ed by addressed device, indicates that current cy-
cle can be shortened.
REF#
Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Consumer-S performs a refresh
cycle on the ISA bus. It is used as an input when
an ISA master owns the bus and is used to trigger
a refresh cycle.
The STPC Consumer-S performs a pseudo hid-
den refresh. It requests the host bus for two host
clocks to drive the refresh address and capture it
in external buffers. The host bus is then relin-
quished while the refresh cycle continues on the
ISA bus.
MASTER#
Add On Card Owns Bus.This signal is
active when an ISA device has been granted bus
ownership.
AEN
Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indi-
cate that a DMA transfer will occur. The enabling
of the signal indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK#
IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal be-
comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
IOCHRDY Channel Ready. IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Consumer-S. The STPC Consumer-S
monitors this signal as an input when performing
an ISA cycle on behalf of the host CPU, DMA
master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Consumer-
S since the access to the system memory can be
considerably delayed due UMA architecture.
ISAOE# Bidirectional OE Control.This signal con-
trols the OE signal of the external transceiver that
connects the IDE DD bus and ISA SA bus.
GPIOCS#
I/O General Purpose Chip Select. This
output signal is used by the external latch on ISA
bus to latch the data on the SD[7:0] bus. The latch
can be use by PMU unit to control the external pe-
ripheral devices or any other desired function.
IRQ_MUX[3:0]
Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They
have to be encoded before connection to the
STPC Consumer-S using ISACLK and ISACLKX2
as the input selection strobes.
Note that IRQ8B, which by convention is connect-
ed to the RTC, is inverted before being sent to the
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