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參數(shù)資料
| 型號： | STPCC0390BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 49/59頁 |
| 文件大?。?/td> | 932K |
| 代理商： | STPCC0390BTC3 |
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BOARD LAYOUT
Issue 1.1 - October 16, 2000
53/59
6.3.8 Data Mask (DQM[7:0])
The data mask load is quite similar to that of the
data signals.
6.3.9 Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For applica-
tions where speed is not so critical series termina-
tion can be used as this will save power. Using a
low impedance such as 50
for these critical trac-
es is recommended as it both reduces the delay
and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals for
unbuffered DIMMs. When using registered DIMMs
the other signals will probably be just as critical as
the address/control signals so to gain maximum
benefit from using registered DIMMs the timings
should also be considered in that situation. Using
lower impedance traces is also beneficial for the
other signals but if their timing is not as critical as
the address/control signals they could use the de-
fault value. Using a lower impedance implies us-
ing wider traces which may have an impact on the
routing of the board.
6.4 SDRAM LAYOUT EXAMPLES
The STPC provides MA, RAS#, CAS#, WE#, CS#,
DQM#, BA0 (MA[11])and MD for SDRAM control.
From 2 to 128 MBytes of main memory are sup-
ported in 1 to 4 banks. All Banks must be 64 bits
wide.
The following memory devices are supported:
4Mbit x 4, 8Mbit x 2 & 16Mbit x 1 or if in the case of
two internal bank chips, 2Mbit x 4 x 2, 4Mbit x 2 x
2 & 8Mbit x 1 x 2 .
The following Figure 6-17 and Figure 6-18, shows
two possible SDRAM organizations based on one
or two bank configurations.
Notes for Figure 6-17 and Figure 6-18;
All buffers must be low skew clock buffers
One clock driver can operate upto four memory
chips.
All the clock lines must follow the rules below;
MCLKI = MCLK0 + MCLK0A
= ......
= MCLK0 + MCLK0D
= MCLK1 + MCLK1A
= ......
= MCLK1 + MCLK1D
This means that all line lengths must go from the
buffer to the memory chips (MCLK1 or MCLK0 or
...) and from the buffer to the STPC (MCLKI) must
be identical.
6.4.1 Host Address to MA bus Mapping
Graphics memory resides at the beginning of
Bank 0. Host memory begins at the top of graphics
memory and extends to the top of populated
SDRAM.
The bank attributes can be retrieved from a lookup
table to select the final SDRAM row and column
address mappings. (Table 6-2). Also Table 6-1
shows the Standard DIMM Pinout for the users
that wish to design with DIMMs.
.
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