參數(shù)資料
型號(hào)： STPCC0390BTC3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁(yè)數(shù)： 27/59頁(yè)
文件大?。?/td> 932K
代理商： STPCC0390BTC3
ELECTRICAL SPECIFICATIONS
Issue 1.1 - October 16, 2000
33/59
11c4 Memory access to 16 bit ISA Slave - 4BCLK
2T
Cycles
11d4 Memory access to 8 bit ISA Slave - 2BCLK
2T
Cycles
11e4
Memory access to 8 bit ISA Slave - Standard 3BCLK
2T
Cycles
124
ALE# asserted before ALE# negated
1T
Cycles
134
ALE# asserted before MEMR#, MEMW# asserted
13a4 Memory Access to 16 bit ISA Slave
2T
Cycles
13b4 Memory Access to 8 bit ISA Slave
2T
Cycles
134
ALE# asserted before SMEMR#, SMEMW# asserted
13c4 Memory Access to 16 bit ISA Slave
2T
Cycles
13d4 Memory Access to 8 bit ISA Slave
2T
Cycles
13e4
ALE# asserted before IOR#, IOW# asserted
2T
Cycles
144
ALE# asserted before AL[23:17]
14a4 Non compressed
15T
Cycles
14b4 Compressed
15T
Cycles
154
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a4 Memory Access to 16 bit ISA Slave- 4 BCLK
11T
Cycles
15e4 Memory Access to 8 bit ISA Slave- Standard Cycle
11T
Cycles
18a4
ALE# negated before LA[23:17] invalid (non compressed)
14T
Cycles
18a4
ALE# negated before LA[23:17] invalid (compressed)
14T
Cycles
224
MEMR#, MEMW# asserted before LA[23:17]
22a4 Memory access to 16 bit ISA Slave.
13T
Cycles
22b4 Memory access to 8 bit ISA Slave.
13T
Cycles
234
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b4 Memory access to 16 bit ISA Slave Standard cycle
9T
Cycles
23e4 Memory access to 8 bit ISA Slave Standard cycle
9T
Cycles
234
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h4 Memory access to 16 bit ISA Slave Standard cycle
9T
Cycles
23l4 Memory access to 16 bit ISA Slave Standard cycle
9T
Cycles
234
IOR#, IOW# asserted before IOR#, IOW # negated
23o4 Memory access to 16 bit ISA Slave Standard cycle
9T
Cycles
23r4 Memory access to 8 bit ISA Slave Standard cycle
9T
Cycles
244
MEMR#, MEMW# asserted before SA[19:0]
24b4 Memory access to 16 bit ISA Slave Standard cycle
10T
Cycles
24d4 Memory access to 8 bit ISA Slave - 3BLCK
10T
Cycles
24e4 Memory access to 8 bit ISA Slave Standard cycle
10T
Cycles
24f4 Memory access to 8 bit ISA Slave - 7BCLK
10T
Cycles
244
SMEMR#, SMEMW# asserted before SA[19:0]
24h Memory access to 16 bit ISA Slave Standard cycle
10T
Cycles
24i4 Memory access to 16 bit ISA Slave - 4BCLK
10T
Cycles
24k4 Memory access to 8 bit ISA Slave - 3BCLK
10T
Cycles
24l4 Memory access to 8 bit ISA Slave Standard cycle
10T
Cycles
244
IOR#, IOW# asserted before SA[19:0]
24o4 I/O access to 16 bit ISA Slave Standard cycle
19T
Cycles
24r4 I/O access to 16 bit ISA Slave Standard cycle
19T
Cycles
254
MEMR#, MEMW# asserted before next ALE# asserted
Table 4-9. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
Note; The signal numbering refers to Table 4-2
Note 4; These timings are extracted from simulations and are not garanteed by testing
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