參數(shù)資料
型號(hào)： STPCC0390BTC3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁(yè)數(shù)： 43/59頁(yè)
文件大?。?/td> 932K
代理商： STPCC0390BTC3
BOARD LAYOUT
48/59
Issue 1.1 - October 16, 2000
from a low skew clock driver with matched routing
lengths. This is shown inFigure 6-11.
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew be-
tween the outputs. The delay through the buffer is
not important so it does not have to be a zero de-
lay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed
can vary between PCB layers the clocks should
be routed in a consistent way. The routing to the
STPC memory input should be longer by 75mm to
compensate for the extra clock routing on the
DIMM. Also a 20pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace im-
pedance (60-75 ohms
). To minimise crosstalk
the clocks should be routed with spacing to adja-
cent tracks of at least twice the clock trace width.
Figure 6-10. DIMM placement
DIMM4
DIMM3
DIMM2
DIMM1
STPC
35mm
15mm
10mm
116mm
SDRAM I/F
Figure 6-11. Clock routing
MCLKO
DIMM CKn input
STPC MCLKI
DIMM CKn input
Low skew clock driver:
L
L+75mm*
20pF
* No additionnal 75mm when SDRAM directly soldered on board
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