參數(shù)資料
型號： STPCC0390BTC3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁數(shù)： 29/59頁
文件大?。?/td> 932K
代理商： STPCC0390BTC3
ELECTRICAL SPECIFICATIONS
Issue 1.1 - October 16, 2000
35/59
41c4
I/O access to 16 bit ISA Slave
6T
Cycles
41d4
I/O access to 8 bit ISA Slave
12T
Cycles
424
SA[19:0] SBHE valid to read data valid
42b4
Memory access to 16 bit ISA Slave Standard cycle
4T
Cycles
42e4
Memory access to 8 bit ISA Slave Standard cycle
10T
Cycles
42h4
I/O access to 16 bit ISA Slave Standard cycle
4T
Cycles
42l4
I/O access to 8 bit ISA Slave Standard cycle
10T
Cycles
474
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW # asserted to IOCHRDY negated
47a4
Memory access to 16 bit ISA Slave
2T
Cycles
47b4
Memory access to 8 bit ISA Slave
5T
Cycles
47c4
I/O access to 16 bit ISA Slave
2T
Cycles
47d4
I/O access to 8 bit ISA Slave
5T
Cycles
484
MEMR#, SMEMR#, IOR# asserted to read data valid
48b4
Memory access to 16 bit ISA Slave Standard Cycle
2T
Cycles
48e4
Memory access to 8 bit ISA Slave Standard Cycle
5T
Cycles
48h4
I/O access to 16 bit ISA Slave Standard Cycle
2T
Cycles
48l4
I/O access to 8 bit ISA Slave Standard Cycle
5T
Cycles
544
IOCHRDY asserted to read data valid
54a4
Memory access to 16 bit ISA Slave
1T(R)/2T(W)
Cycles
54b4
Memory access to 8 bit ISA Slave
1T(R)/2T(W)
Cycles
54c4
I/O access to 16 bit ISA Slave
1T(R)/2T(W)
Cycles
54d4
I/O access to 8 bit ISA Slave
1T(R)/2T(W)
Cycles
55a4
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,
SMEMW#, IOR#, IOW# negated
1T
Cycles
55b4
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
1T
Cycles
564
IOCHRDY asserted to next ALE# asserted
2T
Cycles
574
IOCHRDY asserted to SA[19:0], SBHE invalid
2T
Cycles
584
MEMR#, IOR#, SMEMR# negated to read data invalid
0T
Cycles
594
MEMR#, IOR#, SMEMR# negated to daabus float
0T
Cycles
614
Write data before MEMW# asserted
61a4
Memory access to 16 bit ISA Slave
2T
Cycles
61b4
Memory access to 8 bit ISA Slave (Byte copy at end of
start)
2T
Cycles
614
Write data before SMEMW# asserted
61c4
Memory access to 16 bit ISA Slave
2T
Cycles
61d4
Memory access to 8 bit ISA Slave
2T
Cycles
614
Write Data valid before IOW # asserted
61e4
I/O access to 16 bit ISA Slave
2T
Cycles
61f4
I/O access to 8 bit ISA Slave
2T
Cycles
64a4
MEMW# negated to write data invalid - 16 bit
1T
Cycles
64b4
MEMW# negated to write data invalid - 8 bit
1T
Cycles
64c4
SMEMW# negated to write data invalid - 16 bit
1T
Cycles
64d4
SMEMW# negated to write data invalid - 8 bit
1T
Cycles
64e4
IOW # negated to write data invalid
1T
Cycles
Table 4-9. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
Note; The signal numbering refers to Table 4-2
Note 4; These timings are extracted from simulations and are not garanteed by testing
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