- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98149 > STPCC0390BTC3 (STMICROELECTRONICS) MULTIFUNCTION PERIPHERAL, PBGA388 PDF資料下載
參數(shù)資料
| 型號： | STPCC0390BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 45/59頁 |
| 文件大?。?/td> | 932K |
| 代理商： | STPCC0390BTC3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
GENERAL DESCRIPTION
Issue 1.1 - October 16, 2000
5/59
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win-
dows type displays). The flicker filter is optional
and can be software disabled for use with large
screen area’s of video.
The Video output pipeline of the STPC Consumer-
S interfaces directly to the internal digital TV en-
coder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8 bit output stream, the logic includes a progres-
sive to interlaced scan converter and logic to in-
sert appropriate CCIR656 timing reference codes
into the output stream. It facilitates the high quality
display of VGA or full screen video streams re-
ceived via the Video input port to standard NTSC
or PAL televisions.
The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and “NTSC- 4.43” is
also possible.
The four frame (for PAL) or 2 frame (for NTSC)
burst sequences are internally generated, subcar-
rier generation being performed numerically with
CKREF as reference. Rise and fall times of syn-
chronisation tips and burst envelope are internally
controlled according to the relevant ITU-R and
SMPTE recommendations.
Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous R,G,B and composite CVBS and S-
VHS outputs.
MEMORY CONTROLLER
The STPC handles the memory data (DATA) bus
directly, controlling from 2 to 128 MBytes. The
SDRAM controller supports accesses to the Mem-
ory Banks to/from the CPU (via the host), from the
VIP, to/from the CRTC, to the VIDEO & to/from the
GE. (Banks 0 to 3) which can be populated with ei-
ther single or double sided 72-bit (4 bit parity)
DIMMs. Parity is not supported.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (seeTable 1-1):
The SDRAM Controller supports buffered or un-
buffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type ac-
cess.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
IDE INTERFACE
An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-S. The IDE port is
capable of supporting a total of four devices.
POWER MANAGEMENT
The STPC Consumer-S core is compliant with the
Advanced Power Management (APM) specifica-
tion to provide a standard method by which the
BIOS can control the power used by personal
computers. The Power Management Unit module
(PMU) controls the power consumption providing
a comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency’s
Energy Star Computer Program. The PMU pro-
vides following hardware structures to assist the
software in managing the power consumption by
the system.
- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
- Stand-by timer for detecting lack of system activ-
ity for medium durations
- Suspend timer for detecting lack of system activ-
ity for long durations.
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
Table 1-1. Supported Memory Configs
Memory
Bank
size
Number
Organisation
Device
size
1Mx64
4
1Mx16
16Mbit
2Mx64
8
2Mx8
4Mx64
16
4Mx4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STPCD0110BTC3 | 32-BIT, 100 MHz, MICROPROCESSOR, PBGA388 |
| STPCD0112BTC3 | 32-BIT, 120 MHz, MICROPROCESSOR, PBGA388 |
| STPCI2EEYC | MULTIFUNCTION PERIPHERAL, PBGA516 |
| STPCI2HDYI | MULTIFUNCTION PERIPHERAL, PBGA516 |
| STPCI2HEYI | MULTIFUNCTION PERIPHERAL, PBGA516 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPCC4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STPC CONSUMER-II DATASHEET / X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP |
| STPCC4EEBC | 制造商:STMicroelectronics 功能描述:CONS-II 100MHZ COM - Trays 制造商:STMicroelectronics 功能描述:MULTIFUNCTION PERIPHERAL, PBGA388 |
| STPCC4HEBC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible Information Appliance System-on-Chip |
| STPCC4HEBI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible Information Appliance System-on-Chip |
| STPCC5HEBC | 功能描述:微處理器 - MPU 133MHz x86 Embedded RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復。