參數(shù)資料
型號: STPCC0390BTC3
廠商: STMICROELECTRONICS
元件分類: 外設及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA388
封裝: PLASTIC, BGA-388
文件頁數(shù): 24/59頁
文件大小: 932K
代理商: STPCC0390BTC3
ELECTRICAL SPECIFICATIONS
30/59
Issue 1.1 - October 16, 2000
Table 4-4. PCI Bus AC Timing
Name
Parameter
Min
Max
Unit
t1
PCI_CLKI to any output
-
12.8
ns
t2
Setup to PCICKLI
7.0
-
ns
t3
Hold from PCICLKI
1.0
-
ns
t4
PCICLKI to PCI_GNT# output valid
-
12.0
ns
t5
PCI_REQ# setup to PCI_CLKI
12.0
-
ns
T6
PCI_REQ# hold to PCI_CLKI
0.0
-
ns
Table 4-5. IDE Bus AC Timing
Name
Parameter
Min
Max
Unit
t20
PCI_CLKI to SA[19:8] Active
-
42
ns
t21
PCI_CLKI to RMRTCCS# Active
-
42
ns
t22
PCI_CLKI to KBCS# Active
-
42
ns
t23
PCI_CLKI to RTCRW# Active
-
42
ns
t24
PCI_CLKI to RTCDS Active
-
42
ns
t25
SA[19:8] Input Setup to SIOR# Rising
-10
10
ns
t26
SA[19:8] Input Hold to SIOR# Rising
-10
10
ns
t27
RMRTCCS# Input Setup to SIOR# Rising
-10
10
ns
t28
RMRTCCS# Input Hold to SIOR# Rising
-10
10
ns
t29
KBCS# Input Setup to SIOR# Rising
-10
10
ns
t30
KBCS# Input Hold to SIOR# Rising
-10
10
ns
t31
RTCRW# Input Setup to SIOR# Rising
-10
10
ns
t32
RTCRW# Input Hold to SIOR# Rising
-10
10
ns
t33
RTCDS Input Setup to SIOR# Rising
-10
10
ns
t34
RTCDS Input Hold to SIOR# Rising
-10
10
ns
t35
PCI_CLKI to LA[23:17] Active
-
28
ns
t36
PCI_CLKI to PDACK# Active
-
32
ns
t37
PCI_CLKI to SDACK Active
-
32
ns
t38
PCI_CLKI to PIOR# Active
-
28
ns
t39
PCI_CLKI to PIOW # Active
-
28
ns
t40
PCI_CLKI to SIOR# Active
-
28
ns
t41
PCI_CLKI to SIOW # Active
-
28
ns
Table 4-6. SDRAM Bus AC Timing
Name
Parameter
Min
Max
Unit
t42
MCLKI to RAS#[1:0] Output Valid
-
6.2
ns
t43
MCLKI to CAS#[1:0] Output Valid
-
6.2
ns
t44
MCLKI to CS#[3:0] Output Valid
-
7.6
ns
t45
MCLKI to DQM#[7:0] Output Valid
-
8.1
ns
Note; The figures are extrapolated from silicon characterisation results and design timing analysis
Please refer to STPC Consumer-S Programming Manual for RDCLK settings
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