參數(shù)資料
型號(hào)： STPCC0390BTC3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁(yè)數(shù)： 44/59頁(yè)
文件大?。?/td> 932K
代理商： STPCC0390BTC3
BOARD LAYOUT
Issue 1.1 - October 16, 2000
49/59
For designs which use SDRAMs directly mounted
on the motherboard PCB all the clock trace
lengths should be matched exactly.
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are 2 types of DIMM devices; sin-
gle row and dual row. The dual row devices re-
quire 2 chip select signals to select between the
two rows. A STPC device with 4 chip select control
lines could control either 4 single row DIMMs or 2
dual row DIMMs.
When using DIMM modules, schematics have to
be done carefully in order to avoid data busses
completely crossed on the board. This has to be
checked at the library level. In order to achive lay-
out shown in Figure 6-12, schematics have to im-
plement the crossing described on Figure 6-13.
The DQM signals must be exchanged using the
same order.
Figure 6-12. Optimum data bus layout for DIMM
Figure 6-13. Schematics for optimum data bus layout for DIMM
DIMM
STPC
SDRAM I/F
D[15:00]
D[31:16]
D[47:32]
D[63:48]
MD[31:00]
MD[63:32]
MD[15:00],DQM[1:0]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
DIMM
STPC
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