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參數(shù)資料
| 型號： | STPCC0390BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 18/59頁 |
| 文件大?。?/td> | 932K |
| 代理商： | STPCC0390BTC3 |
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STRAP OPTIONS
Issue 1.1 - October 16, 2000
25/59
3.1.4 HCLK Strap register Configuration Index
5Fh (HCLK_Strap)
Bits 7-6
Reserved.
Bits 5-3 These pins reflect thevalue sampled on
MD[26:24] pins respectively and control the Host
clock frequency synthesizer as follows:
Bit 2-0
Reserved.
This register defaults to the values sampled on
above pins after reset.
The recommended value for these three bits is
110.
3.1.5 Delay Programming For DLL (DLL_Prog)
The bits MD[30:27] are used to set the delay of the
host clock entering the on chip DLL used to gener-
ate PCI_CLKO that is synchronous with HCLK.
Please refer to the STPC Consumer-S Reference
Design Schematics for the appropriate value or
contact your ST application engineer.
3.1.6 HCLKI Programming (HCLK_Prog)
The HCLKI clock signal (the clock that is used in
the ADPC std cell logic) is selected and pro-
grammed through strap values on MD[35:31] &
MD[46:45].
MD[46:45] set the source of the HCLKI and the
programming value if the PLL option is chosen.
MD[46:45]
HCLKI source
CPU to HCLKI skew, MD[35:31] are used to set
the correct skew between the HCLKI and the CPU
clock. MD[35] controls whether the CPU clock
leads (strap to vss) or lags (strap to vdd) the
chipset host clock. MD[34:31] set the value of the
skew between these two clocks. Contact your ST
applications support for the correct value to strap
to these bits. These bits are only enabled when
MD[46:45] == 11.
3.1.7 486 Clock Programming (486_Prog)
The bit MD[40] is used to set the clock multiplica-
tion factor of the 486 core. With the MD[40] pin
pulled low the 486 will run in DX (x1) mode, while
with the MD[40] pin pulled high the 486 will run in
DX2 (x2) mode. The default value of the resistor
on this strap input should be a resister to gnd (DX
mode).
CPU clock tic, MD[43:41] are used to set the
clock tic input value for the 486 core DLL.
The recommended value for these three bits is
010.
Bit 5
Bit 4
Bit 3
Description
000
25 MHz
001
33 MHz
0
1
0
100 MHz
011
50 MHz
100
60 MHz
101
66 MHz
110
75 MHz
111
90 MHz
MD[46] MD[45] HCLKI Source
00
HCLKI PLL enabled & HCLKI frequen-
cy between 16 & 32 MHz
01
HCLKI PLL enabled & HCLKI frequen-
cy between 32 & 64 MHz
10
HCLKI PLL enabled & HCLKI frequen-
cy greater than 64 MHz
11
HCLKI PLL disabled; delay chains se-
lected
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