參數(shù)資料
型號： STPCC0166BTI3
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA388
封裝： PLASTIC, BGA-388
文件頁數(shù)： 39/71頁
文件大?。?/td> 1238K
代理商： STPCC0166BTI3
Obsolete
Product(s)
- Obsolete
Product(s)
ELECTRICAL SPECIFICATIONS
44/71
Issue 2.4 - November 8, 2001
24l
Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
24
IOR#, IOW# asserted before SA[19:0]
24o
I/O access to 16-bit ISA Slave Standard cycle
19T
Cycles
24r
I/O access to 16-bit ISA Slave Standard cycle
19T
Cycles
25
MEMR#, MEMW# asserted before next ALE# asserted
25b
Memory access to 16-bit ISA Slave Standard cycle
10T
Cycles
25d
Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
25
SMEMR#, SMEMW# asserted before next ALE# asserted
25e
Memory access to 16-bit ISA Slave - 2BCLK
10T
Cycles
25f
Memory access to 16-bit ISA Slave Standard cycle
10T
Cycles
25h
Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
25
IOR#, IOW# asserted before next ALE# asserted
25i
I/O access to 16-bit ISA Slave Standard cycle
10T
Cycles
25k
I/O access to 16-bit ISA Slave Standard cycle
10T
Cycles
26
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
26b
Memory access to 16-bit ISA Slave Standard cycle
12T
Cycles
26d
Memory access to 8-bit ISA Slave Standard cycle
12T
Cycles
26
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f
Memory access to 16-bit ISA Slave Standard cycle
12T
Cycles
26h
Memory access to 8-bit ISA Slave Standard cycle
12T
Cycles
26
IOR#, IOW# asserted before next IOR#, IOW# asserted
26i
I/O access to 16-bit ISA Slave Standard cycle
12T
Cycles
26k
I/O access to 8-bit ISA Slave Standard cycle
12T
Cycles
28
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
28a
Memory access to 16-bit ISA Slave
3T
Cycles
28b
Memory access to 8-bit ISA Slave
3T
Cycles
28
Any command negated to IOR#, IOW# asserted
28c
I/O access to ISA Slave
3T
Cycles
29a
MEMR#, MEMW# negated before next ALE# asserted
1T
Cycles
29b
SMEMR#, SMEMW# negated before next ALE# asserted
1T
Cycles
29c
IOR#, IOW# negated before next ALE# asserted
1T
Cycles
33
LA[23:17] valid to IOCHRDY negated
33a
Memory access to 16-bit ISA Slave - 4 BCLK
8T
Cycles
33b
Memory access to 8-bit ISA Slave - 7 BCLK
14T
Cycles
34
LA[23:17] valid to read data valid
34b
Memory access to 16-bit ISA Slave Standard cycle
8T
Cycles
34e
Memory access to 8-bit ISA Slave Standard cycle
14T
Cycles
37
ALE# asserted to IOCHRDY# negated
37a
Memory access to 16-bit ISA Slave - 4 BCLK
6T
Cycles
37b
Memory access to 8-bit ISA Slave - 7 BCLK
12T
Cycles
37c
I/O access to 16-bit ISA Slave - 4 BCLK
6T
Cycles
37d
I/O access to 8-bit ISA Slave - 7 BCLK
12T
Cycles
38
ALE# asserted to read data valid
38b
Memory access to 16-bit ISA Slave Standard Cycle
4T
Cycles
38e
Memory access to 8-bit ISA Slave Standard Cycle
10T
Cycles
38h
I/O access to 16-bit ISA Slave Standard Cycle
4T
Cycles
Table 4-6. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
Note: The signal numbering refers to Table 4-12
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